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[84.46.13.111]) by mx.google.com with ESMTPSA id hi4sm5595918wjb.46.2014.08.25.23.41.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 25 Aug 2014 23:41:05 -0700 (PDT) From: Thierry Reding To: Stephen Warren Subject: [PATCH v3 1/5] of: Add NVIDIA Tegra Legacy Interrupt Controller binding Date: Tue, 26 Aug 2014 08:41:00 +0200 Message-Id: <1409035264-16999-1-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.0.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140825_234129_313156_1A8A3656 X-CRM114-Status: GOOD ( 10.00 ) X-Spam-Score: -0.8 (/) Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by the AVP coprocessor and can also serve as a backup for the ARM Cortex CPU's local interrupt controller (GIC). The LIC is subdivided into multiple identical units, each handling 32 possible interrupt sources. Signed-off-by: Thierry Reding --- Changes in v3: - bracket individual tuples in the "reg" property .../interrupt-controller/nvidia,tegra20-ictlr.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt new file mode 100644 index 000000000000..1639389b7360 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt @@ -0,0 +1,19 @@ +NVIDIA Tegra Legacy Interrupt Controller + +The legacy interrupt controller is divided into units that serve 32 interrupts +each. Tegra20 implements four units, whereas Tegra30 and later implement five. + +Required properties: +- compatible: "nvidia,tegra-ictlr" +- reg: Physical base address and length of the controller's registers. There + should be one entry for each unit. + +Example: + + interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr"; + reg = <0x60004000 0x40>, /* primary controller */ + <0x60004100 0x40>, /* secondary controller */ + <0x60004200 0x40>, /* tertiary controller */ + <0x60004300 0x40>; /* quaternary controller */ + };