From patchwork Fri Aug 29 11:43:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 4810321 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C36BDC0338 for ; Fri, 29 Aug 2014 11:46:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0A5372011D for ; Fri, 29 Aug 2014 11:46:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 308AD200E3 for ; Fri, 29 Aug 2014 11:46:26 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XNKbj-0004ch-7B; Fri, 29 Aug 2014 11:44:43 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XNKbS-0004QZ-Ep for linux-arm-kernel@lists.infradead.org; Fri, 29 Aug 2014 11:44:27 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 08F1674A; Fri, 29 Aug 2014 13:44:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (tra42-5-83-152-246-54.fbx.proxad.net [83.152.246.54]) by mail.free-electrons.com (Postfix) with ESMTPSA id 9FA0A1BF; Fri, 29 Aug 2014 13:44:05 +0200 (CEST) From: Gregory CLEMENT To: Mike Turquette , linux-kernel@vger.kernel.org Subject: [PATCH 2/4] clk: mvebu: armada-370: Fix timer drift caused by the SSCG deviation Date: Fri, 29 Aug 2014 13:43:38 +0200 Message-Id: <1409312620-20631-3-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1409312620-20631-1-git-send-email-gregory.clement@free-electrons.com> References: <1409312620-20631-1-git-send-email-gregory.clement@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140829_044426_675056_A271D0C7 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.0 (+) Cc: Thomas Petazzoni , Andrew Lunn , Jason Cooper , Tawfik Bayouk , Simon Boulay , Arnaud Ebalard , Nadav Haklai , Lior Amsalem , Ezequiel Garcia , Gregory CLEMENT , Raphael Rigo , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This commit activates the SSCG deviation correction for the Armada 370. It uses the optional function introduced by the commit "clk: mvebu: Fix clk frequency value if SSCG is enabled". Without this fix the deviation measured on a Mirabox was of a few second each hour, whereas with this fix it was reduced at around 50ppm (around 4s per day). Signed-off-by: Gregory CLEMENT --- drivers/clk/mvebu/armada-370.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c index bef198a83863..b084a84d8fad 100644 --- a/drivers/clk/mvebu/armada-370.c +++ b/drivers/clk/mvebu/armada-370.c @@ -23,6 +23,7 @@ */ #define SARL 0 /* Low part [0:31] */ +#define SARL_A370_SSCG_ENABLE BIT(10) #define SARL_A370_PCLK_FREQ_OPT 11 #define SARL_A370_PCLK_FREQ_OPT_MASK 0xF #define SARL_A370_FAB_FREQ_OPT 15 @@ -133,10 +134,16 @@ static void __init a370_get_clk_ratio( } } +bool a370_is_sscg_enabled(void __iomem *sar) +{ + return !(readl(sar) & SARL_A370_SSCG_ENABLE); +} + static const struct coreclk_soc_desc a370_coreclks = { .get_tclk_freq = a370_get_tclk_freq, .get_cpu_freq = a370_get_cpu_freq, .get_clk_ratio = a370_get_clk_ratio, + .is_sscg_enabled = a370_is_sscg_enabled, .ratios = a370_coreclk_ratios, .num_ratios = ARRAY_SIZE(a370_coreclk_ratios), };