From patchwork Tue Sep 2 13:00:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 4825431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 27B4EC0338 for ; Tue, 2 Sep 2014 13:07:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E5208201CE for ; Tue, 2 Sep 2014 13:07:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4741B201D5 for ; Tue, 2 Sep 2014 13:07:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XOnkx-0000xq-O0; Tue, 02 Sep 2014 13:04:19 +0000 Received: from mail-wg0-f41.google.com ([74.125.82.41]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XOnkc-0000Y9-3G for linux-arm-kernel@lists.infradead.org; Tue, 02 Sep 2014 13:03:59 +0000 Received: by mail-wg0-f41.google.com with SMTP id l18so6783455wgh.0 for ; Tue, 02 Sep 2014 06:03:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YM45UCfcfZgcd7VkQ6M4fvYTZukQo1WEf9zRJPqExVU=; b=HRw1+/7p7k8VLjhjv6cgUYXPGyrgfrl/UfZL+2tB5+H/mpTizPizvwv78XpZHXX3B5 krFUSsSN4fT1jfkILLVDt023CJhrBxeGg7fww03k9NRTjPse4hCcUBNxxh2Nn5Z74xsg 0K+QFHJ/I0QQwO7UzzSnt4qaWHxZ3zY+DLXk3C5r2kgQYzMra+cSZLb59CABcoXz7rXO 8D7R4ZOI1XBx+wxMegpJa+g+gGpcLIUnEUoqGut5i6roZCBALu1zifLNRca6qXIzjxqv qManU0rhrjiGBZEWyyO+yJ2SjcEtgpHjmvHHNEiLKoqYYlEuzxLLGU56NcwKInvABB9U Ra6A== X-Gm-Message-State: ALoCoQk/FlmEa+WCPRVcpOTXhughENcKajepcpTjncF/ZGJ47hwhXYEYF+VhTMwfbx9rOgWpQo5n X-Received: by 10.194.118.201 with SMTP id ko9mr38069733wjb.26.1409663015820; Tue, 02 Sep 2014 06:03:35 -0700 (PDT) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id ec2sm34928892wib.19.2014.09.02.06.03.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Sep 2014 06:03:35 -0700 (PDT) From: Daniel Thompson To: Russell King Subject: [PATCH v11 10/19] irqchip: gic: Group 0 workaround. Date: Tue, 2 Sep 2014 14:00:44 +0100 Message-Id: <1409662853-29313-11-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1409662853-29313-1-git-send-email-daniel.thompson@linaro.org> References: <1408466769-20004-1-git-send-email-daniel.thompson@linaro.org> <1409662853-29313-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140902_060358_287302_3D058C65 X-CRM114-Status: GOOD ( 16.63 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Catalin Marinas , Jason Cooper , patches@linaro.org, kgdb-bugreport@lists.sourceforge.net, Linus Walleij , Nicolas Pitre , linux-kernel@vger.kernel.org, Frederic Weisbecker , Anton Vorontsov , Ben Dooks , John Stultz , Fabio Estevam , Colin Cross , Thomas Gleixner , kernel-team@android.com, Dave Martin , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP An ARM system based on GICv1 that runs by default in secure mode and uses both group 0 and group 1 interrupts (in order to exploit FIQ) will suffer a problem where the IRQ handler occasionally spuriously acknowledges a group 0 (FIQ) interrupt. This can be prevented by ensuring the IRQ handler makes non-secure memory access to the GIC registers but this is complex because the non-secure bits cannot be apply to 4k pages (the bit is one level up in the page table and applies to 1MB at a time). This workaround uses an alternative approach that spots the spurious acknowledgment and regenerates the FIQ. This keeps the workaround exclusively within the GIC driver (although there is a runtime perforamnce penalty resulting from this approach). Reported-by: Harro Haan Signed-off-by: Daniel Thompson Tested-by: Harro Haan Cc: Thomas Gleixner Cc: Jason Cooper --- drivers/irqchip/irq-gic.c | 52 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 8834749..bda5a91 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -279,14 +279,59 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) #define gic_set_wake NULL #endif +#ifdef CONFIG_FIQ +/* This is a software emulation of the Aliased Interrupt Acknowledge Register + * (GIC_AIAR) found in GICv2+. + */ +static u32 gic_handle_spurious_group_0(struct gic_chip_data *gic, u32 irqstat) +{ + u32 irqnr = irqstat & GICC_IAR_INT_ID_MASK; + void __iomem *dist_base = gic_data_dist_base(gic); + u32 offset, mask; + + if (!gic_data_fiq_enable(gic) || irqnr >= 1021) + return irqstat; + + offset = irqnr / 32 * 4; + mask = 1 << (irqnr % 32); + if (readl_relaxed(dist_base + GIC_DIST_IGROUP + offset) & mask) + return irqstat; + + /* this interrupt must be taken as a FIQ so put it back into the + * pending state and end our own servicing of it. + */ + writel_relaxed(mask, dist_base + GIC_DIST_PENDING_SET + offset); + readl_relaxed(dist_base + GIC_DIST_PENDING_SET + offset); + writel_relaxed(irqstat, gic_data_cpu_base(gic) + GIC_CPU_EOI); + + return 1023; +} + +static u32 gic_ack_irq(struct gic_chip_data *gic) +{ + u32 irqstat; + + local_fiq_disable(); + irqstat = readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); + irqstat = gic_handle_spurious_group_0(gic, irqstat); + local_fiq_enable(); + + return irqstat; +} +#else +static u32 gic_ack_irq(struct gic_chip_data *gic) +{ + return readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); +} +#endif + static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) { u32 irqstat, irqnr; struct gic_chip_data *gic = &gic_data[0]; - void __iomem *cpu_base = gic_data_cpu_base(gic); do { - irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); + irqstat = gic_ack_irq(gic); irqnr = irqstat & GICC_IAR_INT_ID_MASK; if (likely(irqnr > 15 && irqnr < 1021)) { @@ -295,7 +340,8 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) continue; } if (irqnr < 16) { - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); + writel_relaxed(irqstat, + gic_data_cpu_base(gic) + GIC_CPU_EOI); #ifdef CONFIG_SMP handle_IPI(irqnr, regs); #endif