From patchwork Wed Sep 3 08:45:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 4831511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D1391C0338 for ; Wed, 3 Sep 2014 08:53:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F306E201CE for ; Wed, 3 Sep 2014 08:53:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2BFBF201B9 for ; Wed, 3 Sep 2014 08:53:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XP6Cz-00028Z-NJ; Wed, 03 Sep 2014 08:46:29 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XP6CU-0001jI-4B for linux-arm-kernel@lists.infradead.org; Wed, 03 Sep 2014 08:45:59 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id D135C791; Wed, 3 Sep 2014 10:45:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id E7B936D4; Wed, 3 Sep 2014 10:45:39 +0200 (CEST) From: Boris BREZILLON To: Nicolas Ferre , Jean-Christophe Plagniol-Villard , Alexandre Belloni , Andrew Victor , Alessandro Zummo , rtc-linux@googlegroups.com Subject: [PATCH 4/5] rtc: at91sam9: retain slow clock and check its rate Date: Wed, 3 Sep 2014 10:45:33 +0200 Message-Id: <1409733934-14465-5-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1409733934-14465-1-git-send-email-boris.brezillon@free-electrons.com> References: <1409733934-14465-1-git-send-email-boris.brezillon@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140903_014558_346334_20D84EF3 X-CRM114-Status: GOOD ( 14.12 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Boris BREZILLON , linux-kernel@vger.kernel.org, Rob Herring , Kumar Gala , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The RTT block is using the slow clock and expect it to run at 32KHz. Now that we moved to the CCF it's better to retain the clk reference so that the CCF can't disable the slow clock considering it is unused. Signed-off-by: Boris BREZILLON --- drivers/rtc/rtc-at91sam9.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c index 57014b7..5c5093b 100644 --- a/drivers/rtc/rtc-at91sam9.c +++ b/drivers/rtc/rtc-at91sam9.c @@ -21,6 +21,7 @@ #include #include #include +#include /* * This driver uses two configurable hardware resources that live in the @@ -74,6 +75,7 @@ struct sam9_rtc { u32 imr; void __iomem *gpbr; int irq; + struct clk *sclk; }; #define rtt_readl(rtc, field) \ @@ -373,6 +375,25 @@ static int at91_rtc_probe(struct platform_device *pdev) return ret; } + /* Retain slow clk if it is specified in the DT. + * Do not complain if slow clk is missing, but check its rate + * if it is available. + */ + rtc->sclk = devm_clk_get(&pdev->dev, NULL); + if (!IS_ERR(rtc->sclk)) { + if (clk_get_rate(rtc->sclk) != AT91_SLOW_CLOCK) { + dev_err(&pdev->dev, + "Invalid slow clock rate (expecting %lu got %lu)", + (unsigned long)AT91_SLOW_CLOCK, + clk_get_rate(rtc->sclk)); + return -EINVAL; + } + + ret = clk_prepare_enable(rtc->sclk); + if (ret) + return ret; + } + /* NOTE: sam9260 rev A silicon has a ROM bug which resets the * RTT on at least some reboots. If you have that chip, you must * initialize the time from some external source like a GPS, wall @@ -397,6 +418,9 @@ static int at91_rtc_remove(struct platform_device *pdev) /* disable all interrupts */ rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); + if (!IS_ERR(rtc->sclk)) + clk_disable_unprepare(rtc->sclk); + return 0; }