From patchwork Tue Sep 9 06:07:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 4866031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9BB6C9F32E for ; Tue, 9 Sep 2014 06:10:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 69C3020160 for ; Tue, 9 Sep 2014 06:10:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1912020145 for ; Tue, 9 Sep 2014 06:10:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XREba-0001Ug-KI; Tue, 09 Sep 2014 06:08:42 +0000 Received: from mail-pa0-f46.google.com ([209.85.220.46]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XREb5-00019g-G4 for linux-arm-kernel@lists.infradead.org; Tue, 09 Sep 2014 06:08:13 +0000 Received: by mail-pa0-f46.google.com with SMTP id kq14so1698505pab.19 for ; Mon, 08 Sep 2014 23:07:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jN10/xsoQedbt3nZfrW0uq6rrvMT2ZXddlHQd4n9d18=; b=KrRO8pHJlw2e68Gc+NboruGyh8vuJ3xKlSGX/P8uwLrgs9Mz8IzGOJOIMV6s1oh+O4 lt0kOWm5VuCpUAXaZ6gzS2VzY2hn4QfiVis7TAE0w7DCZ2FcTN12dJjuRThGAoku9xmn T8DNnP51PSVKvlcep9zFybi8XOmpY33f6qaUz263t5ezskbONnA2XjyxqUwRKl1jrEZx ck+lL1BjbYD3ciKSJXK6rTAHNQDJeN9kH+eLsp7/A/eYbQ/wO8t4wXymI9JxI4GzrwAa fhga9fwmK35p9CeYwwIfMesi118yhmqZ4hG2LWgv/TFVAX6DoxPs+4MvbFkTbvOxntSq SzOA== X-Gm-Message-State: ALoCoQkqDDCJyYjMXfRgUQoZ6KuFqwnoDlwxXNYCYdBu9y7Gk3E0uzdSRnUR7oZFMHmGbhoTpXMz X-Received: by 10.66.233.226 with SMTP id tz2mr53573781pac.94.1410242870223; Mon, 08 Sep 2014 23:07:50 -0700 (PDT) Received: from tharvey-gw.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id fp6sm10644315pdb.4.2014.09.08.23.07.49 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 08 Sep 2014 23:07:49 -0700 (PDT) From: Tim Harvey To: Shawn Guo Subject: [PATCH 4/6] ARM: dts: imx: ventana: configure padconf for all pins Date: Mon, 8 Sep 2014 23:07:29 -0700 Message-Id: <1410242851-30765-5-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1410242851-30765-1-git-send-email-tharvey@gateworks.com> References: <1410242851-30765-1-git-send-email-tharvey@gateworks.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140908_230811_635263_781FBFED X-CRM114-Status: GOOD ( 10.45 ) X-Spam-Score: -0.7 (/) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Follow the convention of configuring padconf for all pins and not leaving any 0x80000000 to leave them un-configured. Signed-off-by: Tim Harvey --- arch/arm/boot/dts/imx6q-gw5400-a.dts | 22 +++++++++---------- arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 16 +++++++------- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 32 ++++++++++++++-------------- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 40 +++++++++++++++++------------------ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 28 ++++++++++++------------ 5 files changed, 69 insertions(+), 69 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 9687cd8..eb28f63 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -344,18 +344,18 @@ imx6q-gw5400-a { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index fa2cae4..2853a10 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -170,14 +170,14 @@ imx6qdl-gw51xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0001b0b0 /* PCIE_RST# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 53f4a0b..26b1395 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -240,23 +240,23 @@ imx6qdl-gw52xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* MEZZ_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* MEZZ_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 /* VIDDEC_PDN# */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b0b0 /* PHY Reset */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE_RST# */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_PWDN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* USB_SEL_PCI */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* LVDS_TCH# */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_CD# */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 /* UART2_EN# */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 2074df6..e6e298b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -247,25 +247,25 @@ imx6qdl-gw53xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* PCIE6EXP_DIO0 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* PCIE6EXP_DIO1 */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_SHDN */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* HUB_RST# */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIE_WDIS# */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0001b0b0 /* ACCEL_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0001b0b0 /* USBOTG_OC# */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_DET# */ >; }; @@ -301,8 +301,8 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index ab7827a..a366a93 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -336,19 +336,19 @@ imx6qdl-gw54xx { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0001b0b0 /* SPINOR_CS0# */ + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b0b0 /* TOUCH_IRQ# */ + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x4001b0b0 /* USBHUB_RST# */ + MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x4001b0b0 /* MIPI_DIO */ >; }; @@ -384,8 +384,8 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 >; };