| Message ID | 1410277008-20242-1-git-send-email-galak@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sep 9, 2014, at 8:36 AM, Kumar Gala <galak@codeaurora.org> wrote: > Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled. > > Signed-off-by: Kumar Gala <galak@codeaurora.org> > --- > (reposted with Hans on list) > > v4: > * Updated to upstream changes > > drivers/ata/ahci.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Any updates on these patches? - k
Hi, On 09/16/2014 04:09 AM, Kumar Gala wrote: > > On Sep 9, 2014, at 8:36 AM, Kumar Gala <galak@codeaurora.org> wrote: > >> Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled. >> >> Signed-off-by: Kumar Gala <galak@codeaurora.org> >> --- >> (reposted with Hans on list) >> >> v4: >> * Updated to upstream changes >> >> drivers/ata/ahci.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) > > Any updates on these patches? I send you a detailed review of this on 9 September, titled: "Re: [PATCH v4 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver" I'll forward you that mail again right now. Regards, Hans
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 59ae0ee..90156ff 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -53,7 +53,7 @@ enum { AHCI_MAX_PORTS = 32, - AHCI_MAX_CLKS = 4, + AHCI_MAX_CLKS = 5, AHCI_MAX_SG = 168, /* hardware max is 64K */ AHCI_DMA_BOUNDARY = 0xffffffff, AHCI_MAX_CMDS = 32,
Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled. Signed-off-by: Kumar Gala <galak@codeaurora.org> --- (reposted with Hans on list) v4: * Updated to upstream changes drivers/ata/ahci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)