From patchwork Thu Sep 11 20:11:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 4890171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6F0019F35F for ; Thu, 11 Sep 2014 20:15:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6DE63201C0 for ; Thu, 11 Sep 2014 20:15:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE41920204 for ; Thu, 11 Sep 2014 20:15:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XSAkM-0002qO-FZ; Thu, 11 Sep 2014 20:13:38 +0000 Received: from mail-we0-x230.google.com ([2a00:1450:400c:c03::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XSAjW-0001wC-OI for linux-arm-kernel@lists.infradead.org; Thu, 11 Sep 2014 20:12:47 +0000 Received: by mail-we0-f176.google.com with SMTP id q58so7274412wes.21 for ; Thu, 11 Sep 2014 13:12:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=eRXrgvptgdK6Td8U4eZgp97lf3DLFT/cIwIhTBocdPs=; b=W7v1+G+ZqCU1zrgOMvfgeALC/VEWZjHwWee704wYIWHu+JpTJWenz/VFmbssUNryR0 PvhlkcE+G7HgRFkEPQF6VbcUye6tdfxqspvw3qdVto9j8bflcAOflT0q1qXdrnz+Qfa5 Cod1zKCDb0bPlsJTPVqggzAU4XsCXUXxa+gubz3Z4/PqWY0VAfvg1Xv53L0oB01k2bzi ElyS+Z5DBM0qZ6PoxwVZPcffbZRbDyKiDBzG1kEBPwWo8J8OF0Y53xlhC4L/VG9vg3Yk qy2Q29UH2hki3Nfi59JZepIyqtSqh+trDFhFqFITMcKSCDHUvax5X5sYbXWdNpSqJmlm kg8g== X-Received: by 10.180.101.71 with SMTP id fe7mr10355233wib.48.1410466341583; Thu, 11 Sep 2014 13:12:21 -0700 (PDT) Received: from localhost.localdomain (2-238-57-164.ip242.fastwebnet.it. [2.238.57.164]) by mx.google.com with ESMTPSA id c7sm6990655wib.12.2014.09.11.13.12.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 11 Sep 2014 13:12:20 -0700 (PDT) From: Carlo Caione To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, linux@arm.linux.org.uk, robh+dt@kernel.org, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, daniel.lezcano@linaro.org, tglx@linutronix.de, gregkh@linuxfoundation.org, jslaby@suse.cz, grant.likely@linaro.org, b.galvani@gmail.com, maxime.ripard@free-electrons.com, afaerber@suse.de, matthias.bgg@gmail.com Subject: [PATCH v2 8/9] ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS Date: Thu, 11 Sep 2014 22:11:39 +0200 Message-Id: <1410466300-19168-9-git-send-email-carlo@caione.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1410466300-19168-1-git-send-email-carlo@caione.org> References: <1410466300-19168-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140911_131246_960275_CE62319E X-CRM114-Status: GOOD ( 13.62 ) X-Spam-Score: 0.0 (/) Cc: Carlo Caione X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/meson.dtsi | 74 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson6-atv1200.dts | 25 ++++++++++++ arch/arm/boot/dts/meson6.dtsi | 40 +++++++++++++++++++ 4 files changed, 140 insertions(+) create mode 100644 arch/arm/boot/dts/meson.dtsi create mode 100644 arch/arm/boot/dts/meson6-atv1200.dts create mode 100644 arch/arm/boot/dts/meson6.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adb5ed9..4e2bb17 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -154,6 +154,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood) dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood) dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb +dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MXC) += \ imx25-eukrea-mbimxsd25-baseboard.dtb \ diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi new file mode 100644 index 0000000..ace5db8 --- /dev/null +++ b/arch/arm/boot/dts/meson.dtsi @@ -0,0 +1,74 @@ +/* + * Copyright 2014 Carlo Caione + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + }; + + gic: interrupt-controller@c4301000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xc4301000 0x1000>, + <0xc4300100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@c1109940 { + compatible = "amlogic,meson6-timer"; + reg = <0xc1109940 0x14>; + interrupts = <0 10 1>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart_AO: serial@c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_A: serial@c81084c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81084c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_B: serial@c81084dc { + compatible = "amlogic,meson-uart"; + reg = <0xc81084dc 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_C: serial@c8108700 { + compatible = "amlogic,meson-uart"; + reg = <0xc8108700 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + }; +}; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts new file mode 100644 index 0000000..84576aa --- /dev/null +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2014 Carlo Caione + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; +/include/ "meson6.dtsi" + +/ { + model = "Geniatech ATV1200"; + compatible = "geniatech,atv1200"; + + memory { + reg = <0x40000000 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi new file mode 100644 index 0000000..f9d2cb5 --- /dev/null +++ b/arch/arm/boot/dts/meson6.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright 2014 Carlo Caione + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "meson.dtsi" + +/ { + model = "Amlogic Meson6 SoC"; + compatible = "amlogic,meson6"; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x201>; + }; + }; + + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; +}; /* end of / */