From patchwork Thu Sep 11 22:18:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 4890821 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 491FF9F1D3 for ; Thu, 11 Sep 2014 22:15:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 888D320225 for ; Thu, 11 Sep 2014 22:20:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C9DB20221 for ; Thu, 11 Sep 2014 22:20:26 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XSChS-0007QW-JM; Thu, 11 Sep 2014 22:18:46 +0000 Received: from mail-ig0-f201.google.com ([209.85.213.201]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XSChP-0007Gx-6M for linux-arm-kernel@lists.infradead.org; Thu, 11 Sep 2014 22:18:43 +0000 Received: by mail-ig0-f201.google.com with SMTP id l13so5108iga.4 for ; Thu, 11 Sep 2014 15:18:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=wijAFNSWhAV/GOCdxo+rSStq/43IiqKrBiemq4qty1U=; b=NPf6ppyhlrwGrIHptVA5iVePEJqN0pVVatzK79IUqqsbeQAubpNLINKEOARHDgygGA RPpLJIwArpuDZWu3vPz7yfNXQ15i6ze8vQvfignXGwqCQAtS9ZQhsinLC3Y/SVuhjqbT OMwvqKKVh6+RdowgQpfEZKZVZ4xiwhrFMJ3sTboSYAr2Bj/Zhsg95jB5ozS9Dh4Ze+74 UgQ0x2KU5e36ERIMMeZVf33CusGQT9PmIeQjz+lyIlOoD1oJny4Xiur5O6pYM4FdaIPe 2LFy7zGE46aYmDt3mTlvLwpGdLUtScDe0bY8w6fOq6EPUYrkH899dvfSPbfYXbMa7cxi g3Ow== X-Gm-Message-State: ALoCoQmnXnJekJcRfIVa6gFc0isTwIptIIDI+VDXzDqADsXBWEAfXRyT8pD1sbthiMDTZYvi+xrt X-Received: by 10.182.213.105 with SMTP id nr9mr2195728obc.36.1410473899584; Thu, 11 Sep 2014 15:18:19 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id t28si103525yhb.4.2014.09.11.15.18.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Sep 2014 15:18:19 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com ([172.22.162.1]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id hIGUSPT9.1; Thu, 11 Sep 2014 15:18:19 -0700 Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id D57DBA0575; Thu, 11 Sep 2014 15:18:17 -0700 (PDT) From: Sonny Rao To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] clocksource: arch_timer: Fix code to use physical timers when requested Date: Thu, 11 Sep 2014 15:18:15 -0700 Message-Id: <1410473895-6756-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140911_151843_323070_E3A84246 X-CRM114-Status: GOOD ( 18.32 ) X-Spam-Score: -3.2 (---) Cc: Mark Rutland , Lorenzo Pieralisi , Russell King , Sudeep KarkadaNagesha , Catalin Marinas , Daniel Lezcano , Will Deacon , linux-kernel@vger.kernel.org, stable@vger.kernel.org, dianders@chromium.org, Marc Zyngier , Sudeep Holla , Olof Johansson , Thomas Gleixner , Sonny Rao , Stephen Boyd X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a bug fix for using physical arch timers when the arch_timer_use_virtual boolean is false. It restores the arch_counter_get_cntpct() function after removal in 0d651e4e "clocksource: arch_timer: use virtual counters" and completes the implementation of memory mapped access for physical timers, so if a system is trying to use physical timers, it will function properly. We need this on certain ARMv7 systems which are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) One example of such as system is RK3288 where it is much simpler to use the physical counter since there's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Fixes: 0d651e4e65e9 ("clocksource: arch_timer: use virtual counters") Cc: stable@vger.kernel.org Signed-off-by: Sonny Rao Acked-by: Olof Johansson --- v2: Add fixes tag to commit message, cc stable, copy Doug's description of the systems which need this in commit message. --- arch/arm/include/asm/arch_timer.h | 9 +++++++++ arch/arm64/include/asm/arch_timer.h | 10 ++++++++++ drivers/clocksource/arm_arch_timer.c | 30 ++++++++++++++++++++++++++---- 3 files changed, 45 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 0704e0c..e72aa4d 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -78,6 +78,15 @@ static inline u32 arch_timer_get_cntfrq(void) return val; } +static inline u64 arch_counter_get_cntpct(void) +{ + u64 cval; + + isb(); + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); + return cval; +} + static inline u64 arch_counter_get_cntvct(void) { u64 cval; diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 9400596..58657c4 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -135,6 +135,16 @@ static inline void arch_timer_evtstrm_enable(int divider) #endif } +static inline u64 arch_counter_get_cntpct(void) +{ + u64 cval; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cval)); + + return cval; +} + static inline u64 arch_counter_get_cntvct(void) { u64 cval; diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5163ec1..ad723cb 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -30,6 +30,8 @@ #define CNTTIDR 0x08 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) +#define CNTPCT_LO 0x00 +#define CNTPCT_HI 0x04 #define CNTVCT_LO 0x08 #define CNTVCT_HI 0x0c #define CNTFRQ 0x10 @@ -386,6 +388,19 @@ static u64 arch_counter_get_cntvct_mem(void) return ((u64) vct_hi << 32) | vct_lo; } +static u64 arch_counter_get_cntpct_mem(void) +{ + u32 pct_lo, pct_hi, tmp_hi; + + do { + pct_hi = readl_relaxed(arch_counter_base + CNTPCT_HI); + pct_lo = readl_relaxed(arch_counter_base + CNTPCT_LO); + tmp_hi = readl_relaxed(arch_counter_base + CNTPCT_HI); + } while (pct_hi != tmp_hi); + + return ((u64) pct_hi << 32) | pct_lo; +} + /* * Default to cp15 based access because arm64 uses this function for * sched_clock() before DT is probed and the cp15 method is guaranteed @@ -429,10 +444,17 @@ static void __init arch_counter_register(unsigned type) u64 start_count; /* Register the CP15 based counter if we have one */ - if (type & ARCH_CP15_TIMER) - arch_timer_read_counter = arch_counter_get_cntvct; - else - arch_timer_read_counter = arch_counter_get_cntvct_mem; + if (type & ARCH_CP15_TIMER) { + if (arch_timer_use_virtual) + arch_timer_read_counter = arch_counter_get_cntvct; + else + arch_timer_read_counter = arch_counter_get_cntpct; + } else { + if (arch_timer_use_virtual) + arch_timer_read_counter = arch_counter_get_cntvct_mem; + else + arch_timer_read_counter = arch_counter_get_cntpct_mem; + } start_count = arch_timer_read_counter(); clocksource_register_hz(&clocksource_counter, arch_timer_rate);