| Message ID | 1410540486-22243-2-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Chen-Yu, On Sat, Sep 13, 2014 at 12:48:05AM +0800, Chen-Yu Tsai wrote: > Signed-off-by: Chen-Yu Tsai <wens@csie.org> A commit log would be nice here. Is it different from A31? do you know wether later SoCs reuses it? > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++ > 2 files changed, 56 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index 425b109..fb3b7aa 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -50,6 +50,7 @@ Required properties: > "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 > "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 > "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks > + "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 > "allwinner,sun7i-a20-out-clk" - for the external output clocks > "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 > "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 > diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c > index 4a56385..9850887 100644 > --- a/drivers/clk/sunxi/clk-mod0.c > +++ b/drivers/clk/sunxi/clk-mod0.c > @@ -94,6 +94,61 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node) > } > CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); > > +/** > + * sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks > + * MBUS rate is calculated as follows > + * rate = parent_rate / (m + 1); > + */ > + > +static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate, > + u8 *n, u8 *k, u8 *m, u8 *p) > +{ > + u8 div; > + > + /* These clocks can only divide, so we will never be able to achieve > + * frequencies higher than the parent frequency */ This doesn't follow the multi-line comment style. > + if (*freq > parent_rate) > + *freq = parent_rate; > + > + div = DIV_ROUND_UP(parent_rate, *freq); > + > + if (div > 8) > + div = 8; > + > + *freq = parent_rate / div; > + > + /* we were called to round the frequency, we can now return */ > + if (m == NULL) > + return; > + > + *m = div - 1; > +} > + > +static struct clk_factors_config sun8i_a23_mbus_config = { > + .mshift = 0, > + .mwidth = 3, > +}; > + > +static const struct factors_data sun8i_a23_mbus_data __initconst = { > + .enable = 31, > + .mux = 24, > + .table = &sun8i_a23_mbus_config, > + .getter = sun8i_a23_get_mbus_factors, > +}; > + > +static DEFINE_SPINLOCK(sun8i_a23_mbus_lock); > + > +static void __init sun8i_a23_mbus_setup(struct device_node *node) > +{ > + struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data, > + &sun8i_a23_mbus_lock); > + > + /* The MBUS clocks needs to be always enabled */ > + __clk_get(mbus); > + clk_prepare_enable(mbus); > +} > +CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup); > + It looks like it's pretty much stand alone. Would you mind putting it into a file of its own? something like clk-sun8i-mbus.c? Thanks, Maxime
On Mon, Sep 15, 2014 at 4:20 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi Chen-Yu, > > On Sat, Sep 13, 2014 at 12:48:05AM +0800, Chen-Yu Tsai wrote: >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > A commit log would be nice here. Is it different from A31? do you know > wether later SoCs reuses it? I will copy the description from the cover letter. >> --- >> Documentation/devicetree/bindings/clock/sunxi.txt | 1 + >> drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++ >> 2 files changed, 56 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt >> index 425b109..fb3b7aa 100644 >> --- a/Documentation/devicetree/bindings/clock/sunxi.txt >> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt >> @@ -50,6 +50,7 @@ Required properties: >> "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 >> "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 >> "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks >> + "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 >> "allwinner,sun7i-a20-out-clk" - for the external output clocks >> "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 >> "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 >> diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c >> index 4a56385..9850887 100644 >> --- a/drivers/clk/sunxi/clk-mod0.c >> +++ b/drivers/clk/sunxi/clk-mod0.c >> @@ -94,6 +94,61 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node) >> } >> CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); >> >> +/** >> + * sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks >> + * MBUS rate is calculated as follows >> + * rate = parent_rate / (m + 1); >> + */ >> + >> +static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate, >> + u8 *n, u8 *k, u8 *m, u8 *p) >> +{ >> + u8 div; >> + >> + /* These clocks can only divide, so we will never be able to achieve >> + * frequencies higher than the parent frequency */ > > This doesn't follow the multi-line comment style. Will fix. This was copied from clk-sunxi.c though, meaning a few of them might be lying around. >> + if (*freq > parent_rate) >> + *freq = parent_rate; >> + >> + div = DIV_ROUND_UP(parent_rate, *freq); >> + >> + if (div > 8) >> + div = 8; >> + >> + *freq = parent_rate / div; >> + >> + /* we were called to round the frequency, we can now return */ >> + if (m == NULL) >> + return; >> + >> + *m = div - 1; >> +} >> + >> +static struct clk_factors_config sun8i_a23_mbus_config = { >> + .mshift = 0, >> + .mwidth = 3, >> +}; >> + >> +static const struct factors_data sun8i_a23_mbus_data __initconst = { >> + .enable = 31, >> + .mux = 24, >> + .table = &sun8i_a23_mbus_config, >> + .getter = sun8i_a23_get_mbus_factors, >> +}; >> + >> +static DEFINE_SPINLOCK(sun8i_a23_mbus_lock); >> + >> +static void __init sun8i_a23_mbus_setup(struct device_node *node) >> +{ >> + struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data, >> + &sun8i_a23_mbus_lock); >> + >> + /* The MBUS clocks needs to be always enabled */ >> + __clk_get(mbus); >> + clk_prepare_enable(mbus); >> +} >> +CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup); >> + > > It looks like it's pretty much stand alone. Would you mind putting it > into a file of its own? something like clk-sun8i-mbus.c? No problem. Just thought it would fit nicely with the sun4i version. Thanks ChenYu
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 425b109..fb3b7aa 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -50,6 +50,7 @@ Required properties: "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks + "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 "allwinner,sun7i-a20-out-clk" - for the external output clocks "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c index 4a56385..9850887 100644 --- a/drivers/clk/sunxi/clk-mod0.c +++ b/drivers/clk/sunxi/clk-mod0.c @@ -94,6 +94,61 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node) } CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); +/** + * sun8i_a23_get_mbus_factors() - calculates m factor for MBUS clocks + * MBUS rate is calculated as follows + * rate = parent_rate / (m + 1); + */ + +static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate, + u8 *n, u8 *k, u8 *m, u8 *p) +{ + u8 div; + + /* These clocks can only divide, so we will never be able to achieve + * frequencies higher than the parent frequency */ + if (*freq > parent_rate) + *freq = parent_rate; + + div = DIV_ROUND_UP(parent_rate, *freq); + + if (div > 8) + div = 8; + + *freq = parent_rate / div; + + /* we were called to round the frequency, we can now return */ + if (m == NULL) + return; + + *m = div - 1; +} + +static struct clk_factors_config sun8i_a23_mbus_config = { + .mshift = 0, + .mwidth = 3, +}; + +static const struct factors_data sun8i_a23_mbus_data __initconst = { + .enable = 31, + .mux = 24, + .table = &sun8i_a23_mbus_config, + .getter = sun8i_a23_get_mbus_factors, +}; + +static DEFINE_SPINLOCK(sun8i_a23_mbus_lock); + +static void __init sun8i_a23_mbus_setup(struct device_node *node) +{ + struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data, + &sun8i_a23_mbus_lock); + + /* The MBUS clocks needs to be always enabled */ + __clk_get(mbus); + clk_prepare_enable(mbus); +} +CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup); + struct mmc_phase_data { u8 offset; };
Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-mod0.c | 55 +++++++++++++++++++++++ 2 files changed, 56 insertions(+)