From patchwork Tue Sep 16 01:35:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 4914221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 689A79F467 for ; Tue, 16 Sep 2014 01:36:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17DBA20222 for ; Tue, 16 Sep 2014 01:38:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3F2B2014A for ; Tue, 16 Sep 2014 01:38:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XThh3-0000WZ-6c; Tue, 16 Sep 2014 01:36:33 +0000 Received: from mail-bn1on0110.outbound.protection.outlook.com ([157.56.110.110] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XThh0-0000Rl-00 for linux-arm-kernel@lists.infradead.org; Tue, 16 Sep 2014 01:36:30 +0000 Received: from BY2PR03CA066.namprd03.prod.outlook.com (10.141.249.39) by BLUPR03MB341.namprd03.prod.outlook.com (10.141.48.12) with Microsoft SMTP Server (TLS) id 15.0.1034.8; Tue, 16 Sep 2014 01:36:06 +0000 Received: from BY2FFO11FD035.protection.gbl (2a01:111:f400:7c0c::197) by BY2PR03CA066.outlook.office365.com (2a01:111:e400:2c5d::39) with Microsoft SMTP Server (TLS) id 15.0.1029.13 via Frontend Transport; Tue, 16 Sep 2014 01:36:04 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD035.mail.protection.outlook.com (10.1.14.220) with Microsoft SMTP Server (TLS) id 15.0.1019.14 via Frontend Transport; Tue, 16 Sep 2014 01:36:04 +0000 Received: from dragon.ap.freescale.net ([10.192.185.7]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s8G1ZxNR029847; Mon, 15 Sep 2014 18:36:01 -0700 From: Shawn Guo To: Subject: [PATCH] ARM: imx: fix .is_enabled() of shared gate clock Date: Tue, 16 Sep 2014 09:35:33 +0800 Message-ID: <1410831334-7859-1-git-send-email-shawn.guo@freescale.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(31966008)(107046002)(105606002)(6806004)(106466001)(68736004)(83322001)(76482001)(62966002)(4396001)(89996001)(229853001)(104166001)(44976005)(93916002)(50226001)(88136002)(47776003)(84676001)(46102002)(81542002)(81342002)(80022002)(86362001)(77982001)(64706001)(92726001)(87936001)(99396002)(48376002)(33646002)(95666004)(26826002)(110136001)(104016003)(90102001)(74662001)(79102001)(2351001)(102836001)(74502001)(97736003)(50986999)(36756003)(20776003)(92566001)(19580395003)(50466002)(83072002)(19580405001)(21056001)(85306004)(87286001)(85852003)(77156001)(142923001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB341; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB341; X-Forefront-PRVS: 03361FCC43 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140915_183630_199703_E8D8E53D X-CRM114-Status: UNSURE ( 9.38 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) Cc: Fabio Estevam , Shengjiu Wang , stable@vger.kernel.org, Shawn Guo , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit 63288b721a80 ("ARM: imx: fix shared gate clock") attempted to fix an issue with particular enable/disable sequence from two shared gate clocks. But unfortunately, while it partially fixed the issue, it also did something wrong in .is_enabled() function hook. In case of shared gate, the function shouldn't really query the hardware state via share_count, because the function is trying to query the enabling state of the clock in question, not the hardware state which is shared by multiple clocks. Fix the issue by returning the enable_count of the clock itself which is maintained by clock core, in case it's a clock sharing hardware gate with others. As the result, the initialization of share_count per hardware state is not needed now. So remove it. Reported-by: Fabio Estevam Fixes: 63288b721a80 ("ARM: imx: fix shared gate clock") Cc: Signed-off-by: Shawn Guo Tested-by: Fabio Estevam --- Hi arm-soc folks, Please apply it for 3.17. Thanks. Shawn arch/arm/mach-imx/clk-gate2.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 84acdfd1d715..5a75cdc81891 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) struct clk_gate2 *gate = to_clk_gate2(hw); if (gate->share_count) - return !!(*gate->share_count); + return !!__clk_get_enable_count(hw->clk); else return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); } @@ -127,10 +127,6 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, gate->bit_idx = bit_idx; gate->flags = clk_gate2_flags; gate->lock = lock; - - /* Initialize share_count per hardware state */ - if (share_count) - *share_count = clk_gate2_reg_is_enabled(reg, bit_idx) ? 1 : 0; gate->share_count = share_count; init.name = name;