From patchwork Sun Sep 21 18:45:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksij Rempel X-Patchwork-Id: 4944401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C15979F2BB for ; Sun, 21 Sep 2014 18:49:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9F58220221 for ; Sun, 21 Sep 2014 18:49:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EB2620222 for ; Sun, 21 Sep 2014 18:49:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XVmAR-0002Nx-EM; Sun, 21 Sep 2014 18:47:27 +0000 Received: from mout.gmx.net ([212.227.17.21]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XVmA6-0001xO-Kn for linux-arm-kernel@lists.infradead.org; Sun, 21 Sep 2014 18:47:07 +0000 Received: from zwerg.lan ([80.136.218.135]) by mail.gmx.com (mrgmx102) with ESMTPSA (Nemesis) id 0MKKaI-1XU7jS2pcM-001mHW; Sun, 21 Sep 2014 20:46:48 +0200 From: Oleksij Rempel To: linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, mturquette@linaro.org, jason@lakedaemon.net, gregkh@linuxfoundation.org Subject: [PATCH v2 7/8] irqchip: add irq-asm9260 driver Date: Sun, 21 Sep 2014 20:45:50 +0200 Message-Id: <1411325151-15107-6-git-send-email-linux@rempel-privat.de> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411325151-15107-1-git-send-email-linux@rempel-privat.de> References: <1411324904-14881-1-git-send-email-linux@rempel-privat.de> <1411325151-15107-1-git-send-email-linux@rempel-privat.de> X-Provags-ID: V03:K0:MoEoqND9SErl7iY5kznKbMCZZimsXRLtwnHAzCpzOhOEs4Jj3KZ X5xmBu6InSyiwW2WpH/5X6iMxdV0X+2m8QIthNY6kIGdtBCO1fRi8etzWfMSolMdjoqxYZk 9KZ7iXUwkh8yv7SDIvLFd22FpNjMoviWMAAmFUNspHepTeyJPLrt+PTsDIVilJXarOBebxJ YzlfCrCbd5F5/tIYDZLMQ== X-UI-Out-Filterresults: notjunk:1; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140921_114707_067584_C4E9F603 X-CRM114-Status: GOOD ( 19.91 ) X-Spam-Score: -0.3 (/) Cc: Oleksij Rempel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Oleksij Rempel --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-asm9260.c | 257 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 258 insertions(+) create mode 100644 drivers/irqchip/irq-asm9260.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 73052ba..538fb83 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o +obj-$(CONFIG_MACH_ASM9260) += irq-asm9260.o diff --git a/drivers/irqchip/irq-asm9260.c b/drivers/irqchip/irq-asm9260.c new file mode 100644 index 0000000..b90ea7a --- /dev/null +++ b/drivers/irqchip/irq-asm9260.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2014 Oleksij Rempel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irqchip.h" + +/* + * this device provide 4 offsets for each register: + * 0x0 - plain read write mode + * 0x4 - set mode, OR logic. + * 0x8 - clr mode, XOR logic. + * 0xc - togle mode. + */ +#define SET_REG 4 +#define CLR_REG 8 + +#define HW_ICOLL_VECTOR 0x0000 +/* + * bits 31:2 + * This register presents the vector address for the interrupt currently + * active on the CPU IRQ input. Writing to this register notifies the + * interrupt collector that the interrupt service routine for the current + * interrupt has been entered. + * The exception trap should have a LDPC instruction from this address: + * LDPC HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018 + */ + +/* + * The Interrupt Collector Level Acknowledge Register is used by software to + * indicate the completion of an interrupt on a specific level. + * This register is written at the very end of an interrupt service routine. If + * nesting is used then the CPU irq must be turned on before writing to this + * register to avoid a race condition in the CPU interrupt hardware. + */ +#define HW_ICOLL_LEVELACK 0x0010 +#define BM_LEVELn(nr) BIT(nr) + +#define HW_ICOLL_CTRL 0x0020 +/* BM_CTRL_SFTRST and BM_CTRL_CLKGATE are not available on asm9260. */ +#define BM_CTRL_SFTRST BIT(31) +#define BM_CTRL_CLKGATE BIT(30) +/* disable interrupt level nesting */ +#define BM_CTRL_NO_NESTING BIT(19) +/* + * Set this bit to one enable the RISC32-style read side effect associated with + * the vector address register. In this mode, interrupt in-service is signaled + * by the read of the HW_ICOLL_VECTOR register to acquire the interrupt vector + * address. Set this bit to zero for normal operation, in which the ISR signals + * in-service explicitly by means of a write to the HW_ICOLL_VECTOR register. + * 0 - Must Write to Vector register to go in-service. + * 1 - Go in-service as a read side effect + */ +#define BM_CTRL_ARM_RSE_MODE BIT(18) +#define BM_CTRL_IRQ_ENABLE BIT(16) + +#define HW_ICOLL_STAT_OFFSET 0x0030 +/* + * bits 5:0 + * Vector number of current interrupt. Multiply by 4 and add to vector base + * address to obtain the value in HW_ICOLL_VECTOR. + */ + +/* + * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines + * coming from various parts of the chip. Its purpose is to improve diagnostic + * observability. + */ +#define HW_ICOLL_RAW0 0x0040 +#define HW_ICOLL_RAW1 0x0050 + +#define HW_ICOLL_INTERRUPT0 0x0060 +#define HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (HW_ICOLL_INTERRUPTn(n) \ + + SET_REG) +#define HW_ICOLL_INTERRUPTn_CLR(n) (HW_ICOLL_INTERRUPTn(n) \ + + CLR_REG) +/* + * WARNING: Modifying the priority of an enabled interrupt may result in + * undefined behavior. + */ +#define BM_INT_PRIORITY_MASK 0x3 +#define BM_INT_ENABLE BIT(2) +#define BM_INT_SOFTIRQ BIT(3) + +#define BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3) +#define BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \ + BM_ICOLL_INTERRUPTn_SHIFT(n))) + +#define HW_ICOLL_VBASE 0x0160 +/* + * bits 31:2 + * This bitfield holds the upper 30 bits of the base address of the vector + * table. + */ + +#define HW_ICOLL_CLEAR0 0x01d0 +#define HW_ICOLL_CLEAR1 0x01e0 +#define HW_ICOLL_CLEARn(n) (0x01d0 + ((n >> 5) * 0x10) \ + + SET_REG) +#define BM_CLEAR_BIT(n) BIT(n & 0x1f) + +#define HW_ICOLL_UNDEF_VECTOR 0x01f0 +/* Scratchpad */ + +#define ICOLL_NUM_IRQS 64 + +static void __iomem *icoll_base; +static struct irq_domain *icoll_domain; +static int use_cached_level = 1; +static u8 level_cache[ICOLL_NUM_IRQS]; +static DEFINE_MUTEX(icoll_lock); + +static unsigned int irq_get_level(struct irq_data *d) +{ + unsigned int tmp; + + if (use_cached_level) + return level_cache[d->hwirq]; + + tmp = readl_relaxed(icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); + return (tmp >> BM_ICOLL_INTERRUPTn_SHIFT(d->hwirq)) & 0x3; +} + +static void irq_set_level(int hwirq, int level) +{ + if (unlikely(level < 0 || level > 3)) { + pr_err("%s Wrong level (%i) for irq (%i)!", __func__, level, + hwirq); + return; + } + if (use_cached_level) + level_cache[hwirq] = level; + + writel_relaxed(level << BM_ICOLL_INTERRUPTn_SHIFT(hwirq), + icoll_base + HW_ICOLL_INTERRUPTn(hwirq)); +} + +static void icoll_ack_irq(struct irq_data *d) +{ + readl_relaxed(icoll_base + HW_ICOLL_VECTOR); +} + +static void icoll_mask_irq(struct irq_data *d) +{ + writel_relaxed(BM_ICOLL_INTERRUPTn_ENABLE(d->hwirq), + icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq)); +} + +static void icoll_unmask_irq(struct irq_data *d) +{ + u32 level = irq_get_level(d); + + mutex_lock(&icoll_lock); + writel_relaxed(BM_CLEAR_BIT(d->hwirq), + icoll_base + HW_ICOLL_CLEARn(d->hwirq)); + + writel_relaxed(BM_LEVELn(level), icoll_base + HW_ICOLL_LEVELACK); + + writel_relaxed(BM_ICOLL_INTERRUPTn_ENABLE(d->hwirq), + icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); + mutex_unlock(&icoll_lock); +} + +static struct irq_chip asm9260_icoll_chip = { + .irq_ack = icoll_ack_irq, + .irq_mask = icoll_mask_irq, + .irq_unmask = icoll_unmask_irq, +}; + +asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) +{ + u32 hwirq; + + hwirq = readl_relaxed(icoll_base + HW_ICOLL_STAT_OFFSET); + + handle_domain_irq(icoll_domain, hwirq, regs); +} + +static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + irq_set_chip_and_handler(virq, &asm9260_icoll_chip, handle_level_irq); + set_irq_flags(virq, IRQF_VALID); + + return 0; +} + +static struct irq_domain_ops icoll_irq_domain_ops = { + .map = icoll_irq_domain_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init icoll_of_init(struct device_node *np, + struct device_node *interrupt_parent) +{ + struct resource res; + int i; + + if (of_address_to_resource(np, 0, &res)) + panic("%s: unable to get resource", np->full_name); + + if (!request_mem_region(res.start, resource_size(&res), np->name)) + panic("%s: unable to request mem region", np->full_name); + + icoll_base = ioremap_nocache(res.start, resource_size(&res)); + if (!icoll_base) + panic("%s: unable to map resource", np->full_name); + + /* enable IRQ controller */ + writel_relaxed(BM_CTRL_ARM_RSE_MODE | BM_CTRL_IRQ_ENABLE, + icoll_base + HW_ICOLL_CTRL); + + /* + * This ICOLL has no reset option. So, set all priorities + * manually to 0. + */ + for (i = 0; i < 16 * 0x10; i += 0x10) + writel(0, icoll_base + HW_ICOLL_INTERRUPT0 + i); + + icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, + &icoll_irq_domain_ops, NULL); + if (!icoll_domain) + panic("%s: unable add irq domain", np->full_name); + + irq_set_default_host(icoll_domain); + + set_handle_irq(icoll_handle_irq); + + return icoll_domain ? 0 : -ENODEV; +} +IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icall", icoll_of_init);