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[78.53.87.200]) by mx.google.com with ESMTPSA id ky3sm19788016wjb.39.2014.09.24.08.38.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Sep 2014 08:38:06 -0700 (PDT) From: Robert Richter To: Bjorn Helgaas , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH 4/6] pci, thunder: Document PCIe host controller devicetree bindings Date: Wed, 24 Sep 2014 17:37:46 +0200 Message-Id: <1411573068-12952-5-git-send-email-rric@kernel.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1411573068-12952-1-git-send-email-rric@kernel.org> References: <1411573068-12952-1-git-send-email-rric@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140924_083829_439361_4CF005AF X-CRM114-Status: GOOD ( 11.08 ) X-Spam-Score: -0.7 (/) Cc: devicetree@vger.kernel.org, Arnd Bergmann , Liviu Dudau , Will Deacon , linux-kernel@vger.kernel.org, Robert Richter , linux-pci@vger.kernel.org, Sunil Goutham , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sunil Goutham This patch adds documentation for the devicetree bindings used by the Thunder PCI host controller. Signed-off-by: Sunil Goutham Signed-off-by: Robert Richter --- .../devicetree/bindings/pci/cavium,thunder-pci.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cavium,thunder-pci.txt diff --git a/Documentation/devicetree/bindings/pci/cavium,thunder-pci.txt b/Documentation/devicetree/bindings/pci/cavium,thunder-pci.txt new file mode 100644 index 000000000000..c8ff3d2e8630 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cavium,thunder-pci.txt @@ -0,0 +1,32 @@ +* Cavium Thunder PCIe interface + +Required properties: +- compatible: should contain "cavium,thunder-pcie" to identify the core. +- device_type: set to "pci" +- #address-cells: set to <3> +- #size-cells: set to <2> +- #stream-id-cells: set to <1> +- bus-range: PCI bus numbers covered +- reg: base address and length of the pcie configuration space. +- ranges: ranges for the PCI memory regions. +- msi-parent: Link to the hardware entity that serves as the Message + Signaled Interrupt controller for this PCI controller. + +Example: + +SoC specific DT Entry: + + pcie0: pcie0@0x848000000000 { + compatible = "cavium,thunder-pcie"; + device_type = "pci"; + msi-parent = <&its>; + bus-range = <0 255>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem */ + <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>, + <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>; + }; +