| Message ID | 1411807795-6575-8-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Sep 27, 2014 at 04:49:55PM +0800, Chen-Yu Tsai wrote: > The DMA controller requires AHB1 bus clock to be clocked from PLL6. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > arch/arm/boot/dts/sun6i-a31.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi > index caf879d..d7845d3 100644 > --- a/arch/arm/boot/dts/sun6i-a31.dtsi > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi > @@ -353,6 +353,11 @@ > clocks = <&ahb1_gates 6>; > resets = <&ahb1_rst 6>; > #dma-cells = <1>; > + > + /* DMA controller requires AHB1 clocked from PLL6 */ > + assigned-clocks = <&ahb1>; > + assigned-clock-parents = <&pll6 0>; > + assigned-clock-rates = <200000000>; Again, I don't think we need the rate change, and that it's the right place to put it. Maxime
On Tue, Sep 30, 2014 at 11:55 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Sat, Sep 27, 2014 at 04:49:55PM +0800, Chen-Yu Tsai wrote: >> The DMA controller requires AHB1 bus clock to be clocked from PLL6. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> arch/arm/boot/dts/sun6i-a31.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi >> index caf879d..d7845d3 100644 >> --- a/arch/arm/boot/dts/sun6i-a31.dtsi >> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi >> @@ -353,6 +353,11 @@ >> clocks = <&ahb1_gates 6>; >> resets = <&ahb1_rst 6>; >> #dma-cells = <1>; >> + >> + /* DMA controller requires AHB1 clocked from PLL6 */ >> + assigned-clocks = <&ahb1>; >> + assigned-clock-parents = <&pll6 0>; >> + assigned-clock-rates = <200000000>; > > Again, I don't think we need the rate change, and that it's the right > place to put it. I'll drop it. As you mentioned on IRC, re-parenting to pll6 is still required, so I'll keep that bit. Hi, Mike, Is there a recommended way for clock providers to enforce a range on clock rates? Tomeu's patches seem to be for clock consumers. Cheers ChenYu
On Thu, Oct 09, 2014 at 11:01:02AM +0800, Chen-Yu Tsai wrote: > Hi, Mike, > > Is there a recommended way for clock providers to enforce a range > on clock rates? Tomeu's patches seem to be for clock consumers. We discussed that in the past with Mike, and his answer at the time was that every driver should implement that, which I did some time ago. However, it was before Tomeu patches, that indeed enforce constraints at the consumer level, but I'm pretty confident we could add some provider-side constraints quite easily. Maxime
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index caf879d..d7845d3 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -353,6 +353,11 @@ clocks = <&ahb1_gates 6>; resets = <&ahb1_rst 6>; #dma-cells = <1>; + + /* DMA controller requires AHB1 clocked from PLL6 */ + assigned-clocks = <&ahb1>; + assigned-clock-parents = <&pll6 0>; + assigned-clock-rates = <200000000>; }; mmc0: mmc@01c0f000 {
The DMA controller requires AHB1 bus clock to be clocked from PLL6. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun6i-a31.dtsi | 5 +++++ 1 file changed, 5 insertions(+)