From patchwork Mon Sep 29 12:04:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 4995721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E8CACBEEA6 for ; Mon, 29 Sep 2014 12:08:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 98A112025B for ; Mon, 29 Sep 2014 12:08:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F66F201B4 for ; Mon, 29 Sep 2014 12:08:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XYZiJ-0005w7-2B; Mon, 29 Sep 2014 12:05:59 +0000 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XYZiB-0005m7-OV for linux-arm-kernel@lists.infradead.org; Mon, 29 Sep 2014 12:05:52 +0000 Received: by mail-pa0-f46.google.com with SMTP id kq14so4231751pab.19 for ; Mon, 29 Sep 2014 05:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tY+XjyI41i7F0oc0OXrWI0ajB/VQdTeiluJ6BUyp/5Y=; b=UtsWNfwh4X3+7qKhma0RVHqcxoszmOnVYFH6Dc7u0uOSY/gAlBKS+O4Exrwevt2a8t WpvGfPc9+j0MXZS9HM14XANDXMhi2dju31/xZ0GY/a3V0+28xmD/GlN6gcdnIy53pP8w prOhLmSZ8WrGEcwVbgF1KOwd9AZAGmpedc7XUywsHRzsv0GMiC9quF5BQFmsYs56wZ7E wXd4IvqMsS+krind50kI8sRzNKKB6xf+3ysxLYs3gsTilCOBg5p0wAWHakyko+ctmfUm WkfJK3/NcvTI+lRTfSU9R7FIsEDj2sOB0Bum3MVfJQHDmoH2JAso6ZJMyDtpi8B7+xwj nLAQ== X-Received: by 10.68.221.166 with SMTP id qf6mr60523168pbc.12.1411992330447; Mon, 29 Sep 2014 05:05:30 -0700 (PDT) Received: from chunyanzhangubtpc.local.spreadtrum.com ([117.136.0.134]) by mx.google.com with ESMTPSA id nj3sm12181967pdb.70.2014.09.29.05.05.24 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 Sep 2014 05:05:29 -0700 (PDT) From: zhang.lyra@gmail.com To: catalin.marinas@arm.com, gregkh@linuxfoundation.org, ijc+devicetree@hellion.org.uk, jslaby@suse.cz, galak@codeaurora.org, broonie@linaro.org, mark.rutland@arm.com, m-karicheri2@ti.com, pawel.moll@arm.com, artagnon@gmail.com, rrichter@cavium.com, robh+dt@kernel.org, will.deacon@arm.com, orsonzhai@gmail.com, geng.ren@spreadtrum.com, zhizhou.zhang@spreadtrum.com Subject: [PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC Date: Mon, 29 Sep 2014 20:04:49 +0800 Message-Id: <1411992293-7729-3-git-send-email-zhang.lyra@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1411992293-7729-1-git-send-email-zhang.lyra@gmail.com> References: <1411992293-7729-1-git-send-email-zhang.lyra@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140929_050551_827683_1F42E1EA X-CRM114-Status: GOOD ( 12.34 ) X-Spam-Score: -0.8 (/) Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "zhizhou.zhang" Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture. Signed-off-by: zhizhou.zhang Signed-off-by: chunyan.zhang --- arch/arm64/boot/dts/sprd_shark64.dts | 110 ++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 arch/arm64/boot/dts/sprd_shark64.dts diff --git a/arch/arm64/boot/dts/sprd_shark64.dts b/arch/arm64/boot/dts/sprd_shark64.dts new file mode 100644 index 0000000..537cd6d --- /dev/null +++ b/arch/arm64/boot/dts/sprd_shark64.dts @@ -0,0 +1,110 @@ +/* + * dts file for Spreadtrum(sprd) Shark64 SOC + * + * Copyright (C) 2014, Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { + model = "shark64 Board"; + compatible = "sprd,shark64"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlycon=serial_sprd,0x70000000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + reg = <0 0x70000000 0 0x100>; + interrupts = <0 2 0xf04>; + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + reg = <0 0x70100000 0 0x100>; + interrupts = <0 3 0xf04>; + }; +};