From patchwork Wed Oct 8 07:33:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 5051881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 18B7D9F30B for ; Wed, 8 Oct 2014 07:36:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 323D2201BC for ; Wed, 8 Oct 2014 07:36:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3748E201FB for ; Wed, 8 Oct 2014 07:36:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XbllI-0002qx-UJ; Wed, 08 Oct 2014 07:34:16 +0000 Received: from mail-pd0-f201.google.com ([209.85.192.201]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XbllF-0002np-Mn for linux-arm-kernel@lists.infradead.org; Wed, 08 Oct 2014 07:34:14 +0000 Received: by mail-pd0-f201.google.com with SMTP id y10so1381333pdj.4 for ; Wed, 08 Oct 2014 00:33:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/dwUiRewXBW5pkXsF1JIXxqgPUeo6oKJAhvgVwTmtyY=; b=dn8MshLBbYTd3VIW8PJ2ZxyvZYPJxlxHaY6ciFcCH+WsvEet5udSZuYiQIqSX5olnv +Ta4Fh+/WIRtcnn4eG28xuWCBhHnRXxIbdVGMkYHtrJWeZ5HE/2i1YdyO2m1Ffz9cLdR Y805h5BrTI7/BeruD26ovMfBqYeatIsIi+Wn3FepIxma9XDZI4faYHhuwbOCes4M9vY9 Lschaei34PuZuXDzv3qC5+fVxoD0yUVNXuInFumFGocPWKgLcnmU/2fp/0+MjkTbmDSg Ql3rmAWtqGRrpyS0KtaGS+yNXr1dnPnE8gmAOGbml9VvMdEEnqxWgAKdBuDmxEXQFlCa /Rug== X-Gm-Message-State: ALoCoQloc1qdP6dLcZ/Qk1nl2cz2bbvVjQSr+gmFMJ64dJ6VEmyeX0/owTWRVRzwt3TsxboQ5mBn X-Received: by 10.66.141.70 with SMTP id rm6mr5764734pab.37.1412753632259; Wed, 08 Oct 2014 00:33:52 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id n24si982523yha.6.2014.10.08.00.33.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Oct 2014 00:33:52 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com ([172.22.162.1]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id Al8IJZic.1; Wed, 08 Oct 2014 00:33:52 -0700 Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id 54490A0C03; Wed, 8 Oct 2014 00:33:50 -0700 (PDT) From: Sonny Rao To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4] clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers Date: Wed, 8 Oct 2014 00:33:47 -0700 Message-Id: <1412753627-28287-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141008_003413_768984_E11BF71A X-CRM114-Status: GOOD ( 18.44 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Lorenzo Pieralisi , pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Marc Zyngier , Catalin Marinas , Daniel Lezcano , Will Deacon , linux-kernel@vger.kernel.org, robh+dt@kernel.org, Doug Anderson , galak@codeaurora.org, Sudeep Holla , Olof Johansson , Nathan Lynch , Thomas Gleixner , Sonny Rao , Stephen Boyd X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Doug Anderson Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset (CNTVOFF) between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) On systems like the above, it doesn't make sense to use the virtual counter. There's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. This adds an optional property which can inform the kernel of this situation, and firmware is free to remove the property if it is going to initialize the CNTVOFF registers when each CPU comes out of reset. Currently, the best course of action in this case is to use the physical timer, which is why it is important that CNTHCTL hasn't been changed from its reset value and it's a reasonable assumption given that the firmware has never entered HYP mode. Note that it's been said that on ARMv8 systems the firmware and kernel really can't be architected as described above. That means using the physical timer like this really only makes sense for ARMv7 systems. Signed-off-by: Doug Anderson Signed-off-by: Sonny Rao Reviewed-by: Mark Rutland Acked-by: Daniel Lezcano Tested-by: Yingjoe Chen Acked-by: Catalin Marinas --- Changes in v2: - Add "#ifdef CONFIG_ARM" as per Will Deacon Changes in v3: - change property name to arm,cntvoff-not-fw-configured and specify that the value of CNTHCTL.PL1PC(T)EN must still be the reset value of 1 as per Mark Rutland Changes in v4: - change property name to arm,cpu-registers-not-fw-configured and specify that all cpu registers must have architected reset values per Mark Rutland - change from "#ifdef CONFIG_ARM" to "if (IS_ENABLED(CONFIG_ARM))" per Arnd Bergmann --- Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++ drivers/clocksource/arm_arch_timer.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 37b2caf..256b4d8 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -22,6 +22,14 @@ to deliver its interrupts via SPIs. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. +** Optional properties: + +- arm,cpu-registers-not-fw-configured : Firmware does not initialize + any of the generic timer CPU registers, which contain their + architecturally-defined reset values. Only supported for 32-bit + systems which follow the ARMv7 architected reset values. + + Example: timer { diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 8daf056..799139f 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -654,6 +654,14 @@ static void __init arch_timer_init(struct device_node *np) arch_timer_detect_rate(NULL, np); /* + * If we cannot rely on firmware initializing the timer registers then + * we should use the physical timers instead. + */ + if (IS_ENABLED(CONFIG_ARM) && + of_property_read_bool(np, "arm,cpu-registers-not-fw-configured")) + arch_timer_use_virtual = false; + + /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so * that a guest can use the virtual timer instead.