From patchwork Wed Oct 8 07:38:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 5051901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 133769F30B for ; Wed, 8 Oct 2014 07:41:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D793200FE for ; Wed, 8 Oct 2014 07:41:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2D0E200F0 for ; Wed, 8 Oct 2014 07:41:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XblqJ-0005af-N7; Wed, 08 Oct 2014 07:39:27 +0000 Received: from mail-pa0-f73.google.com ([209.85.220.73]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XblqG-0005X5-NA for linux-arm-kernel@lists.infradead.org; Wed, 08 Oct 2014 07:39:25 +0000 Received: by mail-pa0-f73.google.com with SMTP id et14so1832260pad.0 for ; Wed, 08 Oct 2014 00:39:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=tCZH339jSEW6bGDZ1qn9SkeOQNnn3Bc0QTJO/FSqUi4=; b=bwC2lrknBN5SnXQOa2eE6tn9E9e8G81Fnvl/UoNkoELwhRbUESkWezZRUDlQdsRMit ox6/yNAuCw1yRjQDvGHVEty4LXJz/hOCz2krvw4NtLw3eHyllOTF5eQSbkRMyDlnc1iz xe3ijqTlLK5h/eoFk0VtamtPMN3kjB5Rkk/ni+a8CE+ZVo2L8+ElR2B1hy2u7/zHh9o8 zzee8P4WnnED3A0iyKCjTY/j3DzEaqBHk4+6JAk5FnhS5iONnhxuDf0iu81e/k7xzlRh UwGZkOm9cAyrObjgxSxLJNMpIROECuv0fbFH/qsloQhdfARHfg4tSGXDzOxrdO+mrmqC X1cQ== X-Gm-Message-State: ALoCoQk3MFICS737W8y/PIb42E1PFNjfUE+PmsjJZ97nTl9DxCEEpkn7EveMz0UfwPgEGAB7jnfq X-Received: by 10.66.254.202 with SMTP id ak10mr5760857pad.42.1412753943351; Wed, 08 Oct 2014 00:39:03 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id l45si986427yha.2.2014.10.08.00.39.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Oct 2014 00:39:03 -0700 (PDT) Received: from sonnyrao.mtv.corp.google.com ([172.22.162.1]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id Mdnpo6f7.1; Wed, 08 Oct 2014 00:39:03 -0700 Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id 9BA7AA0C03; Wed, 8 Oct 2014 00:39:01 -0700 (PDT) From: Sonny Rao To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4] clocksource: arch_timer: Fix code to use physical timers when requested Date: Wed, 8 Oct 2014 00:38:57 -0700 Message-Id: <1412753937-29343-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141008_003924_794087_E82FA61A X-CRM114-Status: GOOD ( 17.02 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , Lorenzo Pieralisi , Russell King , Sudeep KarkadaNagesha , Catalin Marinas , Daniel Lezcano , Will Deacon , linux-kernel@vger.kernel.org, stable@vger.kernel.org, dianders@chromium.org, Marc Zyngier , Sudeep Holla , Olof Johansson , Thomas Gleixner , Sonny Rao , Stephen Boyd X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a bug fix for using physical arch timers when the arch_timer_use_virtual boolean is false. It restores the arch_counter_get_cntpct() function after removal in 0d651e4e "clocksource: arch_timer: use virtual counters" We need this on certain ARMv7 systems which are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) One example of such as system is RK3288 where it is much simpler to use the physical counter since there's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Fixes: 0d651e4e65e9 ("clocksource: arch_timer: use virtual counters") Cc: stable@vger.kernel.org Signed-off-by: Sonny Rao Acked-by: Olof Johansson --- v2: Add fixes tag to commit message, cc stable, copy Doug's description of the systems which need this in commit message. v3: Don't change the memory-mapped physical timer/counter code v4: remove the memory-mapped physical counter code since it's not used --- arch/arm/include/asm/arch_timer.h | 9 +++++++++ arch/arm64/include/asm/arch_timer.h | 10 ++++++++++ drivers/clocksource/arm_arch_timer.c | 10 +++++++--- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 0704e0c..e72aa4d 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -78,6 +78,15 @@ static inline u32 arch_timer_get_cntfrq(void) return val; } +static inline u64 arch_counter_get_cntpct(void) +{ + u64 cval; + + isb(); + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); + return cval; +} + static inline u64 arch_counter_get_cntvct(void) { u64 cval; diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 9400596..58657c4 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -135,6 +135,16 @@ static inline void arch_timer_evtstrm_enable(int divider) #endif } +static inline u64 arch_counter_get_cntpct(void) +{ + u64 cval; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cval)); + + return cval; +} + static inline u64 arch_counter_get_cntvct(void) { u64 cval; diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 6b50311..799139f 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -429,10 +429,14 @@ static void __init arch_counter_register(unsigned type) u64 start_count; /* Register the CP15 based counter if we have one */ - if (type & ARCH_CP15_TIMER) - arch_timer_read_counter = arch_counter_get_cntvct; - else + if (type & ARCH_CP15_TIMER) { + if (arch_timer_use_virtual) + arch_timer_read_counter = arch_counter_get_cntvct; + else + arch_timer_read_counter = arch_counter_get_cntpct; + } else { arch_timer_read_counter = arch_counter_get_cntvct_mem; + } start_count = arch_timer_read_counter(); clocksource_register_hz(&clocksource_counter, arch_timer_rate);