From patchwork Sat Oct 11 15:41:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 5069151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id ED965C11AC for ; Sat, 11 Oct 2014 15:44:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 10F522018E for ; Sat, 11 Oct 2014 15:44:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2412920165 for ; Sat, 11 Oct 2014 15:44:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XcyoO-0000CX-AK; Sat, 11 Oct 2014 15:42:28 +0000 Received: from mail-wg0-x22e.google.com ([2a00:1450:400c:c00::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xcynf-0008Q7-Tw for linux-arm-kernel@lists.infradead.org; Sat, 11 Oct 2014 15:41:47 +0000 Received: by mail-wg0-f46.google.com with SMTP id l18so5932564wgh.29 for ; Sat, 11 Oct 2014 08:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :content-type:content-transfer-encoding; bh=wgymmSALSykG70eoiQ5XH6d7YFZvtXqJe5EAOVk07do=; b=RJr4jsQpGbHTvRmTqwOPVkoKxMvD35VT1C7k0dw1PPln7F6fypExzZsVKWnOA/KE5K ulkYsrPFJN7lVAB6ut1glNbWFEjcqBj0dqbUf/iRhqLCURPnPuh7pczK+hKN1P5NStgF zolUpSrouVX0v7rgCjS3mi3V4moLkH8900fB5DfFubnU0edB8N79THmuhTKxvTgCoaSF cW3UKDn+XMqbNqU1Y5ZnnACtLPMaShZf0yNykwRwKaqxIoiUhnhTlsA3UHCXIHvsuKTB 3ux7gp24mGEPnirlmuFFtGX2vGxBTFYdtZwjrZ2es7ejlHSp8AIl3KMhw6xr+0nF2Rh7 oWpA== X-Received: by 10.194.110.130 with SMTP id ia2mr2297680wjb.112.1413042080813; Sat, 11 Oct 2014 08:41:20 -0700 (PDT) Received: from topkick.lan (f052024004.adsl.alicedsl.de. [78.52.24.4]) by mx.google.com with ESMTPSA id hp2sm10430553wjb.40.2014.10.11.08.41.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 11 Oct 2014 08:41:19 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Subject: [PATCH 1/5] phy: berlin-sata: Move PHY_BASE into private data struct Date: Sat, 11 Oct 2014 17:41:09 +0200 Message-Id: <1413042073-14253-2-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1413042073-14253-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1413042073-14253-1-git-send-email-sebastian.hesselbarth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141011_084144_124004_BECE965E X-CRM114-Status: GOOD ( 14.91 ) X-Spam-Score: -0.8 (/) Cc: devicetree@vger.kernel.org, =?UTF-8?q?Antoine=20T=C3=A9nart?= , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, Berlin SATA PHY driver assumes PHY_BASE address being constant. While this PHY_BASE is correct for BG2Q, older BG2 PHY_BASE is different. Prepare the driver for BG2 support by moving the phy_base into private driver data. Signed-off-by: Sebastian Hesselbarth --- Cc: Kishon Vijay Abraham I Cc: "Antoine Ténart" Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/phy/phy-berlin-sata.c | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c index 69ced52d72aa..9682b0f66177 100644 --- a/drivers/phy/phy-berlin-sata.c +++ b/drivers/phy/phy-berlin-sata.c @@ -30,7 +30,7 @@ #define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16) #define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19) -#define PHY_BASE 0x200 +#define BG2Q_PHY_BASE 0x200 /* register 0x01 */ #define REF_FREF_SEL_25 BIT(0) @@ -61,15 +61,16 @@ struct phy_berlin_priv { struct clk *clk; struct phy_berlin_desc **phys; unsigned nphys; + u32 phy_base; }; -static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 reg, - u32 mask, u32 val) +static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, + u32 phy_base, u32 reg, u32 mask, u32 val) { u32 regval; /* select register */ - writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR); + writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); /* set bits */ regval = readl(ctrl_reg + PORT_VSR_DATA); @@ -103,17 +104,20 @@ static int phy_berlin_sata_power_on(struct phy *phy) writel(regval, priv->base + HOST_VSA_DATA); /* set PHY mode and ref freq to 25 MHz */ - phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff, - REF_FREF_SEL_25 | PHY_MODE_SATA); + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, + 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA); /* set PHY up to 6 Gbps */ - phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0); + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, + 0x0c00, PHY_GEN_MAX_6_0); /* set 40 bits width */ - phy_berlin_sata_reg_setbits(ctrl_reg, 0x23, 0xc00, DATA_BIT_WIDTH_40); + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, + 0x0c00, DATA_BIT_WIDTH_40); /* use max pll rate */ - phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE); + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, + 0x0000, USE_MAX_PLL_RATE); /* set Gen3 controller speed */ regval = readl(ctrl_reg + PORT_SCR_CTL); @@ -182,9 +186,22 @@ static u32 phy_berlin_power_down_bits[] = { POWER_DOWN_PHY1, }; +static u32 bg2q_sata_phy_base = BG2Q_PHY_BASE; + +static const struct of_device_id phy_berlin_sata_of_match[] = { + { + .compatible = "marvell,berlin2q-sata-phy", + .data = &bg2q_sata_phy_base, + }, + { }, +}; + static int phy_berlin_sata_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const struct of_device_id *match = + of_match_node(phy_berlin_sata_of_match, dev->of_node); + const u32 *phy_base = match->data; struct device_node *child; struct phy *phy; struct phy_provider *phy_provider; @@ -218,6 +235,8 @@ static int phy_berlin_sata_probe(struct platform_device *pdev) if (!priv->phys) return -ENOMEM; + priv->phy_base = *phy_base; + dev_set_drvdata(dev, priv); spin_lock_init(&priv->lock); @@ -264,11 +283,6 @@ static int phy_berlin_sata_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id phy_berlin_sata_of_match[] = { - { .compatible = "marvell,berlin2q-sata-phy" }, - { }, -}; - static struct platform_driver phy_berlin_sata_driver = { .probe = phy_berlin_sata_probe, .driver = {