From patchwork Tue Oct 14 18:35:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 5082021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7F8649F349 for ; Tue, 14 Oct 2014 18:38:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 876A020204 for ; Tue, 14 Oct 2014 18:38:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91BCC201FE for ; Tue, 14 Oct 2014 18:38:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe6xT-0000w4-Rd; Tue, 14 Oct 2014 18:36:31 +0000 Received: from mail-wi0-x229.google.com ([2a00:1450:400c:c05::229]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xe6xB-0000l2-7p for linux-arm-kernel@lists.infradead.org; Tue, 14 Oct 2014 18:36:14 +0000 Received: by mail-wi0-f169.google.com with SMTP id h11so6805870wiw.4 for ; Tue, 14 Oct 2014 11:35:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9R913HWevedQE1rSV9Jiktm8OpuwZB8SBi5n7O0HyU8=; b=rZVeEJgrNuyYNfdsTmO4HtbngsYYRxx9y7x4gk0FcT3SDVyC7HwahjvE6IKrkNJA9y HBoL6LjYM8KI3NMZ12kwKJXoWgrKAIHKt1ItAyR2Sc/QeLqI7sFrnZrlHaDpLyNydrGO /01iQTZsT2Ga15k2ZhYYb+iTA0Gnf+zIB0aaniqa+hoZHkk8vxhFy4LJB1HPq/neDbus f7xxQRtGAhSb4eaZbiqxIxLLENr8XVmTJEZnLBEYLQLu1hZiXeHjfEwGgdhtXn1jP6wp SwW8K9QTpOdZwSxHoDl3hXjwrYNZ6jY/JT9TJpmoWzncPPhdDJfpE/8P2YQgm6tBUUl2 Prdw== X-Received: by 10.180.99.163 with SMTP id er3mr4020156wib.18.1413311751131; Tue, 14 Oct 2014 11:35:51 -0700 (PDT) Received: from nuc.fastwebnet.it (2-238-57-164.ip242.fastwebnet.it. [2.238.57.164]) by mx.google.com with ESMTPSA id pm6sm21078873wjb.36.2014.10.14.11.35.49 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Oct 2014 11:35:50 -0700 (PDT) From: Carlo Caione To: p.zabel@pengutronix.de, grant.likely@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, b.galvani@gmail.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, maxime.ripard@free-electrons.com Subject: [PATCH v2 1/3] ARM: meson: reset: Add reset controller for MesonX SoCs Date: Tue, 14 Oct 2014 20:35:47 +0200 Message-Id: <1413311749-13948-2-git-send-email-carlo@caione.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1413311749-13948-1-git-send-email-carlo@caione.org> References: <1413311749-13948-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141014_113613_433585_DBBA27F9 X-CRM114-Status: GOOD ( 17.45 ) X-Spam-Score: -0.7 (/) Cc: Carlo Caione X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for the reset controller found on the Amlogic MesonX SoCs. For several devices in the AO (Always-On) power domain, it is possible to reset them by programming a specific bit in a register. Signed-off-by: Carlo Caione --- drivers/reset/Makefile | 1 + drivers/reset/reset-meson.c | 142 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-meson.c diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 60fed3d..74f2372 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o +obj-$(CONFIG_ARCH_MESON) += reset-meson.o obj-$(CONFIG_ARCH_STI) += sti/ diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c new file mode 100644 index 0000000..59b58e4 --- /dev/null +++ b/drivers/reset/reset-meson.c @@ -0,0 +1,142 @@ +/* + * Copyright 2014 Carlo Caione + * + * based on + * Steffen Trumtrar Reset Controller driver + * + * Copyright 2014 Steffen Trumtrar + * + * Steffen Trumtrar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MESON_RST_OFFSET 0x00 + +struct meson_reset_data { + spinlock_t lock; + void __iomem *membase; + struct reset_controller_dev rcdev; +}; + +static int meson_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct meson_reset_data *data = container_of(rcdev, + struct meson_reset_data, + rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->membase + MESON_RST_OFFSET); + writel(reg | BIT(id), data->membase + MESON_RST_OFFSET); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int meson_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct meson_reset_data *data = container_of(rcdev, + struct meson_reset_data, + rcdev); + + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->membase + MESON_RST_OFFSET); + writel(reg & ~BIT(id), data->membase + MESON_RST_OFFSET); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int meson_reset_dev(struct reset_controller_dev *rcdev, unsigned long id) +{ + int err; + + err = meson_reset_assert(rcdev, id); + if (err) + return err; + + return meson_reset_deassert(rcdev, id); +} + +static struct reset_control_ops meson_reset_ops = { + .assert = meson_reset_assert, + .deassert = meson_reset_deassert, + .reset = meson_reset_dev, +}; + +static int meson_reset_probe(struct platform_device *pdev) +{ + struct meson_reset_data *data; + struct resource *res; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->membase)) + return PTR_ERR(data->membase); + + spin_lock_init(&data->lock); + + platform_set_drvdata(pdev, data); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = BITS_PER_LONG; + data->rcdev.ops = &meson_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + + return reset_controller_register(&data->rcdev); +} + +static int meson_reset_remove(struct platform_device *pdev) +{ + struct meson_reset_data *data = platform_get_drvdata(pdev); + + reset_controller_unregister(&data->rcdev); + + return 0; +} + +static const struct of_device_id meson_reset_dt_ids[] = { + { .compatible = "amlogic,meson6-rst-mgr-ao", }, + { /* sentinel */ }, +}; + +static struct platform_driver meson_reset_driver = { + .probe = meson_reset_probe, + .remove = meson_reset_remove, + .driver = { + .name = "meson-reset", + .of_match_table = meson_reset_dt_ids, + }, +}; +module_platform_driver(meson_reset_driver); + +MODULE_AUTHOR("Carlo Caione "); +MODULE_DESCRIPTION("Meson Reset Controller Driver"); +MODULE_LICENSE("GPL");