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[80.116.41.133]) by mx.google.com with ESMTPSA id bc5sm19561685wjb.14.2014.10.14.14.23.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Oct 2014 14:23:43 -0700 (PDT) From: Beniamino Galvani To: Linus Walleij Subject: [PATCH v2 2/3] pinctrl: meson: add device tree bindings documentation Date: Tue, 14 Oct 2014 23:21:53 +0200 Message-Id: <1413321714-25931-3-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1413321714-25931-1-git-send-email-b.galvani@gmail.com> References: <1413321714-25931-1-git-send-email-b.galvani@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141014_142407_326615_1EB83891 X-CRM114-Status: GOOD ( 13.23 ) X-Spam-Score: -0.1 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Victor Wan , Pawel Moll , Ian Campbell , linux-kernel@vger.kernel.org, Beniamino Galvani , Rob Herring , Kumar Gala , Carlo Caione , Jerry Cao , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree bindings documentation for Amlogic Meson pinmux and GPIO controller. Signed-off-by: Beniamino Galvani --- .../devicetree/bindings/pinctrl/meson,pinctrl.txt | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt new file mode 100644 index 0000000..6645fa6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -0,0 +1,79 @@ +* Amlogic Meson pinmux controller + +Pins are organized in banks; all banks except AO are controlled by the +same set of registers, while the AO bank uses a dedicated register +range. The device tree uses sub-nodes to represent set of banks which +share the same address space. + +Required properties for the root node: + - compatible: "amlogic,meson8-pinctrl" + - reg: address and size of the common registers controlling gpio irq + functionality + +Required properties for gpio sub-nodes: + - reg: should contain address and size for mux, pull-enable, pull and + gpio register sets + - reg-names: an array of strings describing the "reg" entries. Must + contain "mux", "pull" and "gpio". "pull-enable" is optional and + when it is missing the "pull" registers are used instead + - gpio-controller: identifies the node as a gpio controller + - #gpio-cells: must be 2 + +Valid gpio sub-nodes name are: + - "banks" for the standard banks + - "ao-bank" for the AO bank which belong to the special always-on + power domain + +Required properties for configuration nodes: + - pins: the name of a pin group. The list of all available groups can + be found in driver sources. + - function: the name of a function to activate for the specified set + of groups. The list of all available functions can be found in + driver sources. + +Example: + + pinctrl: pinctrl@c1109880 { + compatible = "amlogic,meson8-pinctrl"; + reg = <0xc1109880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@c11080b0 { + reg = <0xc11080b0 0x28>, + <0xc11080e4 0x18>, + <0xc1108120 0x18>, + <0xc1108030 0x30>; + reg-names = "mux", "pull-enable", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_ao: ao-bank@c1108030 { + reg = <0xc8100014 0x4>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + nand { + nand { + pins = "nand_io", "nand_io_ce0", "nand_io_ce1", + "nand_io_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_clk", "nand_dqs", + "nand_ce2", "nand_ce3"; + function = "nand"; + }; + }; + + uart_ao_a: uart_ao_a { + uart_ao_a { + pins = "uart_tx_ao_a", "uart_rx_ao_a"; + "uart_cts_ao_a", "uart_rts_ao_a"; + function = "uart_ao"; + }; + }; + };