From patchwork Fri Oct 17 20:33:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tthayer@opensource.altera.com X-Patchwork-Id: 5099011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8DDDFC11AC for ; Fri, 17 Oct 2014 20:37:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A6AA1201C7 for ; Fri, 17 Oct 2014 20:37:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDDBF201C0 for ; Fri, 17 Oct 2014 20:37:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XfEFF-0003AS-T1; Fri, 17 Oct 2014 20:35:29 +0000 Received: from mail-bl2on0091.outbound.protection.outlook.com ([65.55.169.91] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XfEE7-0000z6-DG for linux-arm-kernel@lists.infradead.org; Fri, 17 Oct 2014 20:34:20 +0000 Received: from dinh-ubuntu.altera.com (64.129.157.38) by BN1PR03MB124.namprd03.prod.outlook.com (10.255.201.23) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Fri, 17 Oct 2014 20:34:12 +0000 From: To: , , , , , , , , , Subject: [PATCHv2 4/4] arm: dts: Add Altera L2 Cache and OCRAM EDAC Date: Fri, 17 Oct 2014 15:33:48 -0500 Message-ID: <1413578029-13205-5-git-send-email-tthayer@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1413578029-13205-1-git-send-email-tthayer@opensource.altera.com> References: <1413578029-13205-1-git-send-email-tthayer@opensource.altera.com> MIME-Version: 1.0 X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: DM2PR00CA0029.namprd00.prod.outlook.com (25.160.243.39) To BN1PR03MB124.namprd03.prod.outlook.com (10.255.201.23) X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BN1PR03MB124; X-Exchange-Antispam-Report-Test: UriScan:; X-Forefront-PRVS: 0367A50BB1 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(6009001)(189002)(199003)(106356001)(81156004)(48376002)(87976001)(76482002)(77156001)(88136002)(62966002)(19300405004)(87286001)(66066001)(64706001)(95666004)(53416004)(229853001)(33646002)(47776003)(107046002)(85306004)(20776003)(31966008)(89996001)(85852003)(50466002)(105586002)(42186005)(102836001)(104166001)(46102003)(15975445006)(80022003)(40100003)(97736003)(19580405001)(122386002)(19580395003)(77096002)(93916002)(99396003)(76176999)(86152002)(86362001)(92566001)(4396001)(50986999)(2201001)(69596002)(101416001)(15202345003)(21056001)(92726001)(50226001)(120916001)(921003)(1121002)(562404015); DIR:OUT; SFP:1101; SCL:1; SRVR:BN1PR03MB124; H:dinh-ubuntu.altera.com; FPR:; MLV:sfv; PTR:InfoNoRecords; MX:1; A:0; LANG:en; X-OriginatorOrg: opensource.altera.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141017_133419_549523_AF000539 X-CRM114-Status: UNSURE ( 9.64 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) Cc: devicetree@vger.kernel.org, tthayer@altera.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tthayer.linux@gmail.com, tthayer@opensource.altera.com, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly. http://www.spinics.net/lists/devicetree/msg51117.html Signed-off-by: Thor Thayer --- v2: Remove OCRAM declaration and reference prior patch. --- .../bindings/arm/altera/socfpga-l2-edac.txt | 15 +++++++++++++++ .../bindings/arm/altera/socfpga-ocram-edac.txt | 16 ++++++++++++++++ arch/arm/boot/dts/socfpga.dtsi | 15 ++++++++++++++- 3 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt new file mode 100644 index 0000000..35b19e3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt @@ -0,0 +1,15 @@ +Altera SoCFPGA L2 cache Error Detection and Correction [EDAC] + +Required Properties: +- compatible : Should be "altr,l2-edac" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. Note the rising edge type. + +Example: + + l2edac@ffd08140 { + compatible = "altr,l2-edac"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt new file mode 100644 index 0000000..31ab205 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt @@ -0,0 +1,16 @@ +Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC] + +OCRAM ECC Required Properties: +- compatible : Should be "altr,ocram-edac" +- reg : Address and size for ECC error interrupt clear registers. +- iram : phandle to On-Chip RAM definition. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. Note the rising edge type. + +Example: + ocramedac@ffd08144 { + compatible = "altr,ocram-edac"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6af96ed..32c63a3 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -618,8 +618,21 @@ interrupts = <0 39 4>; }; + l2edac@ffd08140 { + compatible = "altr,l2-edac"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; + + ocramedac@ffd08144 { + compatible = "altr,ocram-edac"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; + L2: l2-cache@fffef000 { - compatible = "arm,pl310-cache"; + compatible = "arm,pl310-cache", "syscon"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; cache-unified;