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[79.13.250.188]) by mx.google.com with ESMTPSA id lm9sm11506012wjc.45.2014.10.20.04.19.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Oct 2014 04:19:51 -0700 (PDT) From: Carlo Caione To: p.zabel@pengutronix.de, grant.likely@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, b.galvani@gmail.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, maxime.ripard@free-electrons.com Subject: [PATCH v3 1/3] ARM: meson: reset: Add reset controller for MesonX SoCs Date: Mon, 20 Oct 2014 13:19:43 +0200 Message-Id: <1413803985-8363-2-git-send-email-carlo@caione.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1413803985-8363-1-git-send-email-carlo@caione.org> References: <1413803985-8363-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141020_042015_077107_0584599C X-CRM114-Status: GOOD ( 21.08 ) X-Spam-Score: 0.0 (/) Cc: Carlo Caione X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for the reset controller found on the Amlogic MesonX SoCs. For several devices in the AO (Always-On) power domain, it is possible to reset them by programming a specific bit in a register. Signed-off-by: Carlo Caione --- Hi Philipp, from the documentation and the sources I have, it seems that in the register together with the bits for resetting the ICs there are also bits for turning the ICs on and off. I really wanted to avoid create a new of_xlate function just to map the reset IDs to the correct bit in the register so I left the nr_resets to BITS_PER_LONG and I'm using the default of_xlate. This way I can also avoid to use obscure reset IDs to be remapped when I can use directly the bit number in the register as reset ID. --- drivers/reset/Makefile | 1 + drivers/reset/reset-meson.c | 138 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 drivers/reset/reset-meson.c diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 60fed3d..74f2372 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o +obj-$(CONFIG_ARCH_MESON) += reset-meson.o obj-$(CONFIG_ARCH_STI) += sti/ diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c new file mode 100644 index 0000000..4435630 --- /dev/null +++ b/drivers/reset/reset-meson.c @@ -0,0 +1,138 @@ +/* + * Copyright 2014 Carlo Caione + * + * based on + * Socfpga Reset Controller driver + * + * Copyright 2014 Steffen Trumtrar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct meson_reset_data { + spinlock_t lock; + void __iomem *membase; + struct reset_controller_dev rcdev; +}; + +static int meson_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct meson_reset_data *data = container_of(rcdev, + struct meson_reset_data, + rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->membase); + writel(reg | BIT(id), data->membase); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int meson_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct meson_reset_data *data = container_of(rcdev, + struct meson_reset_data, + rcdev); + + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->membase); + writel(reg & ~BIT(id), data->membase); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int meson_reset_dev(struct reset_controller_dev *rcdev, unsigned long id) +{ + int err; + + err = meson_reset_assert(rcdev, id); + if (err) + return err; + + return meson_reset_deassert(rcdev, id); +} + +static struct reset_control_ops meson_reset_ops = { + .assert = meson_reset_assert, + .deassert = meson_reset_deassert, + .reset = meson_reset_dev, +}; + +static int meson_reset_probe(struct platform_device *pdev) +{ + struct meson_reset_data *data; + struct resource *res; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->membase)) + return PTR_ERR(data->membase); + + spin_lock_init(&data->lock); + + platform_set_drvdata(pdev, data); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = BITS_PER_LONG; + data->rcdev.ops = &meson_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + + return reset_controller_register(&data->rcdev); +} + +static int meson_reset_remove(struct platform_device *pdev) +{ + struct meson_reset_data *data = platform_get_drvdata(pdev); + + reset_controller_unregister(&data->rcdev); + + return 0; +} + +static const struct of_device_id meson_reset_dt_ids[] = { + { .compatible = "amlogic,meson6-rst-mgr-ao", }, + { /* sentinel */ }, +}; + +static struct platform_driver meson_reset_driver = { + .probe = meson_reset_probe, + .remove = meson_reset_remove, + .driver = { + .name = "meson-reset", + .of_match_table = meson_reset_dt_ids, + }, +}; +module_platform_driver(meson_reset_driver); + +MODULE_AUTHOR("Carlo Caione "); +MODULE_DESCRIPTION("Meson Reset Controller Driver"); +MODULE_LICENSE("GPL");