From patchwork Mon Oct 20 11:41:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 5104701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 90D39C11AC for ; Mon, 20 Oct 2014 11:36:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5CE3B201F7 for ; Mon, 20 Oct 2014 11:35:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20D25201D3 for ; Mon, 20 Oct 2014 11:35:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgBCw-0005eA-1z; Mon, 20 Oct 2014 11:33:02 +0000 Received: from mailout1.samsung.com ([203.254.224.24]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgBBR-0004Dy-Ks for linux-arm-kernel@lists.infradead.org; Mon, 20 Oct 2014 11:31:31 +0000 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NDQ0078TQNWRBE0@mailout1.samsung.com> for linux-arm-kernel@lists.infradead.org; Mon, 20 Oct 2014 20:31:08 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id B7.91.18484.C72F4445; Mon, 20 Oct 2014 20:31:08 +0900 (KST) X-AuditID: cbfee68f-f791c6d000004834-bf-5444f27cfec8 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 57.61.09430.B72F4445; Mon, 20 Oct 2014 20:31:07 +0900 (KST) Received: from localhost.localdomain ([107.108.73.37]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NDQ00DCWQKPVAT0@mmp2.samsung.com>; Mon, 20 Oct 2014 20:31:07 +0900 (KST) From: Thomas Abraham To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v11 6/6] clk: samsung: remove unused clock aliases and update clock flags Date: Mon, 20 Oct 2014 17:11:21 +0530 Message-id: <1413805281-6269-7-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.6.6.rc2 In-reply-to: <1413805281-6269-6-git-send-email-thomas.ab@samsung.com> References: <1413805281-6269-1-git-send-email-thomas.ab@samsung.com> <1413805281-6269-2-git-send-email-thomas.ab@samsung.com> <1413805281-6269-3-git-send-email-thomas.ab@samsung.com> <1413805281-6269-4-git-send-email-thomas.ab@samsung.com> <1413805281-6269-5-git-send-email-thomas.ab@samsung.com> <1413805281-6269-6-git-send-email-thomas.ab@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsWyRsSkRrfmk0uIwa+p7BbXvzxntfj/6DWr Re+Cq2wWbx5uZrTY9Pgaq8Xn3iOMFjPO72OyeDrhIptFxzJGi1W7/jBabPzq4cDtsXPWXXaP O9f2sHlsXlLv0bdlFaPH9mvzmD0+b5ILYIvisklJzcksSy3St0vgytg66SRzwRfvislXXrM1 MN5x6GLk5JAQMJHY9nQxK4QtJnHh3nq2LkYuDiGBpYwS297uY4QpOnm1ESoxnVFi07UPLBBO G5PE96MnwarYBHQkbrz5DWaLCDhJfDtyjQmkiFngAaPExkVN7CAJYYFoiQ0bL4LtYxFQldh6 uxGsgVfAReLoz6vsEOuUJDb0HmUCsTkFXCVWn+5ghtj2mkliSdtaRhBHQmAXu8TG3x3sEJME JL5NPgR0EwdQQlZi0wFmiEGSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGxXnFibnFpXrpecn7u JkZgZJz+96x/B+PdA9aHGAU4GJV4eHeYuYQIsSaWFVfmHmI0BdowkVlKNDkfGH95JfGGxmZG FqYmpsZG5pZmSuK8C6V+BgsJpCeWpGanphakFsUXleakFh9iZOLglGpgnDr789Yf36fcnrR5 1uUeo9DkRyYdV+tn9ZvHvFJoPJV6WvPopLlf22eFaotONLlh3Kz2kilpebjg7mqrq1O+eOyO ORR4tmVmjszz1IN+i1Y8XHZ+jcdB0SytUxn7MywaFXs+yHC8m3yz6/fJDrsW9Udvz7G2FIe/ TD7o5H4u9+UfYaGbKgukq5RYijMSDbWYi4oTAf5eLGSHAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsVy+t9jQd3qTy4hBj9WWVtc//Kc1eL/o9es Fr0LrrJZvHm4mdFi0+NrrBafe48wWsw4v4/J4umEi2wWHcsYLVbt+sNosfGrhwO3x85Zd9k9 7lzbw+axeUm9R9+WVYwe26/NY/b4vEkugC2qgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTM wFDX0NLCXEkhLzE31VbJxSdA1y0zB+g6JYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFw PUYGaCBhDWPG1kknmQu+eFdMvvKarYHxjkMXIyeHhICJxMmrjWwQtpjEhXvrgWwuDiGB6YwS m659YIFw2pgkvh89yQhSxSagI3HjzW8wW0TASeLbkWtMIEXMAg8YJTYuamIHSQgLREts2HiR FcRmEVCV2Hq7EayBV8BF4ujPq+wQ65QkNvQeZQKxOQVcJVaf7mCG2PaaSWJJ21rGCYy8CxgZ VjGKphYkFxQnpeca6RUn5haX5qXrJefnbmIEx90z6R2MqxosDjEKcDAq8fDuMHMJEWJNLCuu zD3EKMHBrCTC6/AGKMSbklhZlVqUH19UmpNafIjRFOisicxSosn5wJSQVxJvaGxibmpsamli YWJmqSTOe7DVOlBIID2xJDU7NbUgtQimj4mDU6qBcd2mxtyOuTqyzX7GP+Z+s66WLnBVO2XI mN3s5Th/qbXAJe78En2B6c13k+YG3Om7qcgSYbWixq3KTkrFNKCo3WLPqolxE5Yvnq7acrth 9owlz+PXzH86SeuMR8ECcaEG3SuPXiqxdf7RnbZUWt9z/aLO34yW67601f42vqn3xkNJKGOB t4esEktxRqKhFnNRcSIAGo8jGtECAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141020_043130_002225_7EEDCEAE X-CRM114-Status: GOOD ( 11.07 ) X-Spam-Score: -6.4 (------) Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, heiko@sntech.de, viresh.kumar@linaro.org, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags. Cc: Tomasz Figa Signed-off-by: Thomas Abraham Acked-by: Viresh Kumar Acked-by: Mike Turquette Tested-by: Javier Martinez Canillas Tested-by: Chander Kashyap --- drivers/clk/samsung/clk-exynos4.c | 48 +++++++++++++++++----------------- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++----- drivers/clk/samsung/clk-exynos5420.c | 27 ++++++++++++------ 3 files changed, 53 insertions(+), 41 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 9af5767..3731fc7 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1), MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", CLKOUT_CMU_RIGHTBUS, 8, 6), - DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), - DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3), - DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3), - DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), - DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), - DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), - DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3), - DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), - DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), + DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), @@ -769,7 +779,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), + DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, CLK_SET_RATE_PARENT, 0), DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, @@ -1186,17 +1197,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 0), }; -static struct samsung_clock_alias exynos4_aliases[] __initdata = { +static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { ALIAS(CLK_MOUT_CORE, NULL, "moutcore"), ALIAS(CLK_ARM_CLK, NULL, "armclk"), ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"), -}; - -static struct samsung_clock_alias exynos4210_aliases[] __initdata = { - ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"), -}; - -static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"), }; @@ -1463,8 +1467,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4210_div_clks)); samsung_clk_register_gate(ctx, exynos4210_gate_clks, ARRAY_SIZE(exynos4210_gate_clks)); - samsung_clk_register_alias(ctx, exynos4210_aliases, - ARRAY_SIZE(exynos4210_aliases)); samsung_clk_register_fixed_factor(ctx, exynos4210_fixed_factor_clks, ARRAY_SIZE(exynos4210_fixed_factor_clks)); @@ -1486,9 +1488,6 @@ static void __init exynos4_clk_init(struct device_node *np, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); } - samsung_clk_register_alias(ctx, exynos4_aliases, - ARRAY_SIZE(exynos4_aliases)); - exynos4_core_down_clock(soc); exynos4_clk_sleep_init(); @@ -1499,6 +1498,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", _get_rate("sclk_apll"), _get_rate("sclk_mpll"), _get_rate("sclk_epll"), _get_rate("sclk_vpll"), + exynos4_soc == EXYNOS4210 ? _get_rate("armclk") : _get_rate("div_core2")); } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e19e365..1d958f1 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { /* * CMU_CPU */ - MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0, "mout_apll"), - MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY), /* * CMU_CORE */ - MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), + MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), /* * CMU_TOP @@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { /* * CMU_CPU */ - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), /* * CMU_TOP @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_of_add_provider(np, ctx); pr_info("Exynos5250: clock setup completed, armclk=%ld\n", - _get_rate("div_arm2")); + _get_rate("armclk")); } CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index d7ef36a..fcf365d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), - MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), - MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), - MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), - MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), + MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, + CLK_MUX_READ_ONLY), + MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0, + CLK_MUX_READ_ONLY), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), @@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { }; static struct samsung_div_clock exynos5x_div_clks[] __initdata = { - DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), - DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), - DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), - DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), - DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), + DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), + DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3, + CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),