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Tue, 21 Oct 2014 14:45:33 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/7] clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks Date: Tue, 21 Oct 2014 11:13:54 +0530 Message-id: <1413870237-1821-5-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1413870237-1821-1-git-send-email-a.kesavan@samsung.com> References: <1413870237-1821-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsWyRsSkRvfvJ9cQg/ajchbvl/UwWsw/co7V YtPja6wWM87vY7JYtO0/s8X/PTvYLVbt+sPowO6xZt4aRo+ds+6ye2xa1cnmsXlJvcfnTXIB rFFcNimpOZllqUX6dglcGXd7L7AVzJCqWDn/LUsD42fRLkZODgkBE4n7+14zQ9hiEhfurWfr YuTiEBJYyijxcflcVpiiVc8Ps0AkpjNKzFrWwgzh9DFJ/O/bxAhSxSagJ7Hg31ewUSICGhJT uh6zgxQxC2xjlPi26jwbSEJYIEZixeZpYEUsAqoSra93ga3gFXCR2HXtLVADB9A6BYk5k2xA TE4BV4ln+ytAKoSAKr4svgp2nYTAPHaJSZ8/skOMEZD4NvkQC0SrrMSmA1DfSEocXHGDZQKj 8AJGhlWMoqkFyQXFSelFxnrFibnFpXnpesn5uZsYgUF++t+z/h2Mdw9YH2IU4GBU4uGNWOIa IsSaWFZcmXuI0RRow0RmKdHkfGAs5ZXEGxqbGVmYmpgaG5lbmimJ8y6U+hksJJCeWJKanZpa kFoUX1Sak1p8iJGJg1OqgXGj1lH7bS+919go3/PSThc+EMDKe9e7yznr3YyvE3r9deMEu0od Pk7li6n3sZ047arjDMkvgvunnvfcECTgVcrTfLti9YbT/qqWC63KNytvXdu/54Hr8oKadJFT movZU30Sr/89tlTZuUxkwwMJzWeP2KznbN8Rwvjwy//uzi3moTczGLOUtyqxFGckGmoxFxUn AgBYVWGIbQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCIsWRmVeSWpSXmKPExsVy+t9jQd2/n1xDDHb9FbF4v6yH0WL+kXOs FpseX2O1mHF+H5PFom3/mS3+79nBbrFq1x9GB3aPNfPWMHrsnHWX3WPTqk42j81L6j0+b5IL YI1qYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQdcvMATpD SaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhYw5hxt/cCW8EMqYqV89+yNDB+ Fu1i5OSQEDCRWPX8MAuELSZx4d56ti5GLg4hgemMErOWtTBDOH1MEv/7NjGCVLEJ6Eks+PeV GcQWEdCQmNL1mB2kiFlgG6PEt1Xn2UASwgIxEis2TwMrYhFQlWh9vYsVxOYVcJHYde0tUAMH 0DoFiTmTbEBMTgFXiWf7K0AqhIAqviy+yjaBkXcBI8MqRtHUguSC4qT0XCO94sTc4tK8dL3k /NxNjOAYeia9g3FVg8UhRgEORiUe3oglriFCrIllxZW5hxglOJiVRHj/xgCFeFMSK6tSi/Lj i0pzUosPMZoC3TSRWUo0OR8Y33kl8YbGJuamxqaWJhYmZpZK4rwHW60DhQTSE0tSs1NTC1KL YPqYODilGhg7vjjfLOxNqymXVNyVOCHJfXvV2vcmxtHN1vcur2193Ox59+4sU8eIxdnhjYmr hUuzZofOivZsvP1MvOvb1f1et9SifssfXVXqO9vdgJn5guGG9uqyDpbVOsJmj/+7R+w6frx/ bnVzzJzalmOty9ZreGyMO5TVx3N/ZyZv6ULHBbbfn6hlySuxFGckGmoxFxUnAgBiKrVOtwIA AA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141020_224556_658116_970FD2D7 X-CRM114-Status: GOOD ( 10.69 ) X-Spam-Score: -6.4 (------) Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, robh@kernel.org, catalin.marinas@arm.com, tomasz.figa@gmail.com, Naveen Krishna Ch X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Naveen Krishna Ch Add clock support for the watchdog timer, pwm timer and thermal management unit IPs in Exynos7. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos7.c | 14 ++++++++++++++ include/dt-bindings/clock/exynos7-clk.h | 9 +++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 3a30f43..17e5cf4 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -486,9 +486,12 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = { ENABLE_PCLK_PERIC0, 14, 0, 0), GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", ENABLE_PCLK_PERIC0, 16, 0, 0), + GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 21, 0, 0), GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", ENABLE_SCLK_PERIC0, 16, 0, 0), + GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), }; static struct samsung_cmu_info peric0_cmu_info __initdata = { @@ -586,7 +589,9 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", /* Register Offset definitions for CMU_PERIS (0x10040000) */ #define MUX_SEL_PERIS 0x0200 +#define ENABLE_PCLK_PERIS 0x0900 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 +#define ENABLE_SCLK_PERIS 0x0A00 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 /* List of parent clocks for Muxes in CMU_PERIS */ @@ -594,7 +599,9 @@ PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; static unsigned long peris_clk_regs[] __initdata = { MUX_SEL_PERIS, + ENABLE_PCLK_PERIS, ENABLE_PCLK_PERIS_SECURE_CHIPID, + ENABLE_SCLK_PERIS, ENABLE_SCLK_PERIS_SECURE_CHIPID, }; @@ -604,10 +611,17 @@ static struct samsung_mux_clock peris_mux_clks[] __initdata = { }; static struct samsung_gate_clock peris_gate_clks[] __initdata = { + GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", + ENABLE_PCLK_PERIS, 6, 0, 0), + GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", + ENABLE_PCLK_PERIS, 10, 0, 0), + GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), + + GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), }; static struct samsung_cmu_info peris_cmu_info __initdata = { diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 3227679..28c8aa7 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -53,7 +53,9 @@ #define PCLK_HSI2C9 7 #define PCLK_HSI2C10 8 #define PCLK_HSI2C11 9 -#define PERIC0_NR_CLK 10 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PERIC0_NR_CLK 12 /* PERIC1 */ #define PCLK_UART1 1 @@ -72,7 +74,10 @@ /* PERIS */ #define PCLK_CHIPID 1 #define SCLK_CHIPID 2 -#define PERIS_NR_CLK 3 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 /* FSYS0 */ #define ACLK_MMC2 1