From patchwork Tue Oct 21 06:49:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 5110791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A43419F349 for ; Tue, 21 Oct 2014 06:52:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8070120148 for ; Tue, 21 Oct 2014 06:52:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 95C8F200EC for ; Tue, 21 Oct 2014 06:52:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgTGe-00056U-Cx; Tue, 21 Oct 2014 06:50:04 +0000 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgTGS-0004zN-5v for linux-arm-kernel@lists.infradead.org; Tue, 21 Oct 2014 06:49:53 +0000 Received: from mirror2.csie.ntu.edu.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (Authenticated sender: b93043) by smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id B28E820532; Tue, 21 Oct 2014 14:49:29 +0800 (CST) Received: by mirror2.csie.ntu.edu.tw (Postfix, from userid 1000) id 9225B5F9A3; Tue, 21 Oct 2014 14:49:29 +0800 (CST) From: Chen-Yu Tsai To: Lee Jones , Samuel Ortiz , Maxime Ripard , =?UTF-8?q?Emilio=20L=C3=B3pez?= , Mike Turquette Subject: [RFC 3/3] ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodes Date: Tue, 21 Oct 2014 14:49:27 +0800 Message-Id: <1413874167-6479-4-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1413874167-6479-1-git-send-email-wens@csie.org> References: <1413874167-6479-1-git-send-email-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141020_234952_484078_CED25472 X-CRM114-Status: UNSURE ( 8.44 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.1 (--) Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the PRCM clocks and reset controls to the A80 dtsi. The list of apbs clock gates is incomplete. Tests show that bits 0~20 are mutable. We will need documents from Allwinner to complete the support. Also update clock and reset phandles for r_uart. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun9i-a80.dtsi | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 2a1c10d..1f3da34 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -418,13 +418,58 @@ interrupts = <0 36 4>; }; + prcm@08001400 { + compatible = "allwinner,sun9i-a80-prcm"; + reg = <0x08001400 0x200>; + + cpus_clk: cpus_clk { + compatible = "allwinner,sun6i-a31-ar100-clk"; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll4>; + clock-output-names = "cpus"; + }; + + ahbs: ahbs_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&cpus_clk>; + clock-output-names = "ahbs"; + }; + + apbs: apbs_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahbs>; + clock-output-names = "apbs"; + }; + + apbs_gates: apbs_gates_clk { + compatible = "allwinner,sun9i-a80-apbs-gates-clk"; + #clock-cells = <1>; + clocks = <&apbs>; + clock-output-names = "apbs_pio", "apbs_ir", + "apbs_timer", "apbs_rsb", + "apbs_uart", "apbs_1wire", + "apbs_i2c", "apbs_i2s0", + "apbs_i2s1"; + }; + + apbs_rst: apbs_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + r_uart: serial@08002800 { compatible = "snps,dw-apb-uart"; reg = <0x08002800 0x400>; interrupts = <0 38 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apbs_gates 4>; + resets = <&apbs_rst 4>; status = "disabled"; }; };