From patchwork Tue Oct 28 11:18:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 5175361 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BBF84C11AC for ; Tue, 28 Oct 2014 11:22:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C0429201ED for ; Tue, 28 Oct 2014 11:22:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D9481201CD for ; Tue, 28 Oct 2014 11:22:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xj4pI-0004yj-Po; Tue, 28 Oct 2014 11:20:36 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xj4pF-0004pa-Je for linux-arm-kernel@lists.infradead.org; Tue, 28 Oct 2014 11:20:34 +0000 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NE500GF5JHNA130@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 28 Oct 2014 20:20:11 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 40.24.18167.BEB7F445; Tue, 28 Oct 2014 20:20:11 +0900 (KST) X-AuditID: cbfee690-f79ab6d0000046f7-a0-544f7beb5bf3 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 02.4A.20081.BEB7F445; Tue, 28 Oct 2014 20:20:11 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NE500HJQJFER800@mmp1.samsung.com>; Tue, 28 Oct 2014 20:20:11 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, s.nawrocki@samsung.com Subject: [PATCH v3 1/5] clk: samsung: exynos7: add clocks for I2C block Date: Tue, 28 Oct 2014 16:48:51 +0530 Message-id: <1414495135-25588-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1414495135-25588-1-git-send-email-a.kesavan@samsung.com> References: <1414495135-25588-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBLMWRmVeSWpSXmKPExsWyRsSkSvd1tX+IwcaZShabHl9jtZhxfh+T xaJt/5ktDr9pZ7VYtesPowOrx85Zd9k9Ni+p9+jbsorR4/MmuQCWKC6blNSczLLUIn27BK6M S1fesRfMlqrYeVurgXGKWBcjJ4eEgInEk+bVzBC2mMSFe+vZuhi5OIQEljJKnP+1hBGmaP6C VqjEIkaJDzfPMEI4fUwSXcs3g7WzCehJLPj3Fcjm4BARcJA43SoIEmYWyJN4/vcOO4gtLOAu cWrOR1YQm0VAVaJ/xgQwm1fAVeJhwxdWkFYJAQWJOZNsQMKcAm4ST3u+gU0XAirpnPmOCeKe ZnaJw306EGMEJL5NPsQC0SorsekA1C+SEgdX3GCZwCi8gJFhFaNoakFyQXFSepGJXnFibnFp Xrpecn7uJkZgAJ/+92zCDsZ7B6wPMQpwMCrx8Bo89AsRYk0sK67MPcRoCrRhIrOUaHI+ME7y SuINjc2MLExNTI2NzC3NlMR5X0v9DBYSSE8sSc1OTS1ILYovKs1JLT7EyMTBKdXA2De9verU 9PrcxvDFTK/WLWASZCzwfezFwno44vRmreb6ZXeEn7/YrWv+2nGilSLXG59535cUyGppvb83 n9VKerHscdHog2anMub1LLm68JKddm6PdXeDtUmK6NIz5qGcjO3Slvcsfwqv2L+bZ1qo6laV mdeZ5Hf7hcXPCvLp9d6/3MdoU81WJZbijERDLeai4kQAosF2r1sCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMIsWRmVeSWpSXmKPExsVy+t9jAd3X1f4hBlumi1tsenyN1WLG+X1M Fou2/We2OPymndVi1a4/jA6sHjtn3WX32Lyk3qNvyypGj8+b5AJYohoYbTJSE1NSixRS85Lz UzLz0m2VvIPjneNNzQwMdQ0tLcyVFPISc1NtlVx8AnTdMnOA9ioplCXmlAKFAhKLi5X07TBN CA1x07WAaYzQ9Q0JgusxMkADCWsYMy5decdeMFuqYudtrQbGKWJdjJwcEgImEvMXtLJB2GIS F+6tB7K5OIQEFjFKfLh5hhHC6WOS6Fq+mRmkik1AT2LBv69ANgeHiICDxOlWQZAws0CexPO/ d9hBbGEBd4lTcz6ygtgsAqoS/TMmgNm8Aq4SDxu+sIK0SggoSMyZZAMS5hRwk3ja8w1suhBQ SefMd0wTGHkXMDKsYhRNLUguKE5KzzXUK07MLS7NS9dLzs/dxAiOkGdSOxhXNlgcYhTgYFTi 4TV46BcixJpYVlyZe4hRgoNZSYQ3IsY/RIg3JbGyKrUoP76oNCe1+BCjKdBRE5mlRJPzgdGb VxJvaGxibmpsamliYWJmqSTOe6DVOlBIID2xJDU7NbUgtQimj4mDU6qBUeT3T8vv004anPx6 cYsax9wTd1waVHJ6HkR8jPZk6u1S1l0v/fp2qwW7fW/AOoPFu87P+LkhRO9sFpfonzhuvjsZ HxeWFlr9+MnNf6F22q55qjtmbu67uuuTbNx6DX2N+Md/li6935OUsbHpjXzvROm3E/ym3Enc Wpj17GV/osM1y/SJYluNpiuxFGckGmoxFxUnAgDpavhzpgIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141028_042033_879877_8687CEEE X-CRM114-Status: UNSURE ( 9.63 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.6 (-----) Cc: Naveen Krishna Ch , linux-samsung-soc@vger.kernel.org, tomasz.figa@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Naveen Krishna Ch Exynos7 supports 12 I2C channels, add the I2C gate clocks to support them. Signed-off-by: Naveen Krishna Ch Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos7.c | 24 ++++++++++++++++++++++++ include/dt-bindings/clock/exynos7-clk.h | 16 ++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 54206d4..c700f65 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -290,6 +290,20 @@ static struct samsung_mux_clock peric0_mux_clks[] __initdata = { }; static struct samsung_gate_clock peric0_gate_clks[] __initdata = { + GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 8, 0, 0), + GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 9, 0, 0), + GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 10, 0, 0), + GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 11, 0, 0), + GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 12, 0, 0), + GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 13, 0, 0), + GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", + ENABLE_PCLK_PERIC0, 14, 0, 0), GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", ENABLE_PCLK_PERIC0, 16, 0, 0), @@ -347,6 +361,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = { }; static struct samsung_gate_clock peric1_gate_clks[] __initdata = { + GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 4, 0, 0), + GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 5, 0, 0), + GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 6, 0, 0), + GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 7, 0, 0), + GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", + ENABLE_PCLK_PERIC1, 8, 0, 0), GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", ENABLE_PCLK_PERIC1, 9, 0, 0), GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 00fd6de..6d07b6f 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -30,7 +30,14 @@ /* PERIC0 */ #define PCLK_UART0 1 #define SCLK_UART0 2 -#define PERIC0_NR_CLK 3 +#define PCLK_HSI2C0 3 +#define PCLK_HSI2C1 4 +#define PCLK_HSI2C4 5 +#define PCLK_HSI2C5 6 +#define PCLK_HSI2C9 7 +#define PCLK_HSI2C10 8 +#define PCLK_HSI2C11 9 +#define PERIC0_NR_CLK 10 /* PERIC1 */ #define PCLK_UART1 1 @@ -39,7 +46,12 @@ #define SCLK_UART1 4 #define SCLK_UART2 5 #define SCLK_UART3 6 -#define PERIC1_NR_CLK 7 +#define PCLK_HSI2C2 7 +#define PCLK_HSI2C3 8 +#define PCLK_HSI2C6 9 +#define PCLK_HSI2C7 10 +#define PCLK_HSI2C8 11 +#define PERIC1_NR_CLK 12 /* PERIS */ #define PCLK_CHIPID 1