From patchwork Wed Oct 29 11:52:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 5187161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2BCEFC11AD for ; Wed, 29 Oct 2014 11:57:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 59B5420253 for ; Wed, 29 Oct 2014 11:57:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A7962022D for ; Wed, 29 Oct 2014 11:57:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XjRq6-0004Dx-KW; Wed, 29 Oct 2014 11:54:58 +0000 Received: from mail-pa0-f65.google.com ([209.85.220.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XjRoW-0002mu-FL; Wed, 29 Oct 2014 11:53:21 +0000 Received: by mail-pa0-f65.google.com with SMTP id eu11so1993130pac.4 for ; Wed, 29 Oct 2014 04:52:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nt/P3+rJQx9a/HcGzt5cLBAUlBx+SbI6gb7RbKIGn2A=; b=mGYo0TdgK5qBZf+3Vfk9gJAReScGOlWceJ1+3ZBI6fxsELSOlivHAeRQfG31C6bR0s 454+G06E8qOtq2G8YuXZuEl0+SCswXXpFurK6tatXrme5knfBzexEd7gw9U+mkHqvpiC sSWQKihxhz3yVG/MrA4F9pviieLlZ6+zu/+ExuXQTXtdhgDw7n6DyExNqOJcoBJcJcxt lzV5uok7mHTZl3D5Cndu2VPbrdKA9+K52SzCW9rA0U7kGQ4lxOsHG4phApUlLdQVhPiq 4fW9HagNa5ebJMYBjMY/OIe1FlezOie91QrVo5LhqM/zke6emrYWHvErF6013rjre4bQ Tk0w== X-Received: by 10.67.3.202 with SMTP id by10mr9643990pad.81.1414583578976; Wed, 29 Oct 2014 04:52:58 -0700 (PDT) Received: from localhost.localdomain ([104.166.103.139]) by mx.google.com with ESMTPSA id tc8sm3441987pab.19.2014.10.29.04.52.53 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 29 Oct 2014 04:52:57 -0700 (PDT) From: Chris Zhong To: heiko@sntech.de, dianders@chromium.org Subject: [PATCH v6 3/7] clk: rockchip: RK3288: add suspend and resume Date: Wed, 29 Oct 2014 19:52:01 +0800 Message-Id: <1414583525-17395-4-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414583525-17395-1-git-send-email-zyw@rock-chips.com> References: <1414583525-17395-1-git-send-email-zyw@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141029_045320_595204_FA397CCE X-CRM114-Status: GOOD ( 16.08 ) X-Spam-Score: -0.5 (/) Cc: Mark Rutland , Russell King , Pawel Moll , Ian Campbell , Linus Walleij , khilman@kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Rob Herring , Chris Zhong , mturquette@linaro.org, Tony Xie , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP save and restore some clks, which might be changed in suspend. Signed-off-by: Tony Xie Signed-off-by: Chris Zhong Reviewed-by: Doug Anderson Tested-by: Doug Anderson --- Changes in v6: - modify comments Changes in v5: - modify comments Changes in v4: None Changes in v3: None Changes in v2: - __raw_readl/__raw_writel replaced by readl_relaxed/writel_relaxed drivers/clk/rockchip/clk-rk3288.c | 60 +++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 2327829..66a9cb0 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "clk.h" @@ -762,6 +763,64 @@ static const char *rk3288_critical_clocks[] __initconst = { "hclk_peri", }; +#ifdef CONFIG_PM_SLEEP +static void __iomem *rk3288_cru_base; + +/* Some CRU registers will be reset in maskrom when the system + * wakes up from fastboot. + * So save them before suspend, restore them after resume. + */ +static const int rk3288_saved_cru_reg_ids[] = { + RK3288_MODE_CON, + RK3288_CLKSEL_CON(0), + RK3288_CLKSEL_CON(1), + RK3288_CLKSEL_CON(10), + RK3288_CLKSEL_CON(33), + RK3288_CLKSEL_CON(37), +}; + +static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; + +static int rk3288_clk_suspend(void) +{ + int i, reg_id; + + for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) { + reg_id = rk3288_saved_cru_reg_ids[i]; + + rk3288_saved_cru_regs[i] = + readl_relaxed(rk3288_cru_base + reg_id); + } + return 0; +} + +static void rk3288_clk_resume(void) +{ + int i, reg_id; + + for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) { + reg_id = rk3288_saved_cru_reg_ids[i]; + + writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000, + rk3288_cru_base + reg_id); + } +} + +static struct syscore_ops rk3288_clk_syscore_ops = { + .suspend = rk3288_clk_suspend, + .resume = rk3288_clk_resume, +}; + +static void rk3288_clk_sleep_init(void __iomem *reg_base) +{ + rk3288_cru_base = reg_base; + register_syscore_ops(&rk3288_clk_syscore_ops); +} + +#else /* CONFIG_PM_SLEEP */ +static void rk3288_clk_sleep_init(void __iomem *reg_base) {} +#endif + static void __init rk3288_clk_init(struct device_node *np) { void __iomem *reg_base; @@ -810,5 +869,6 @@ static void __init rk3288_clk_init(struct device_node *np) ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_register_restart_notifier(RK3288_GLB_SRST_FST); + rk3288_clk_sleep_init(reg_base); } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);