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X-Spam-Score: -0.0 (/) Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tthayer.linux@gmail.com, tthayer@opensource.altera.com, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer Adding the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly. http://www.spinics.net/lists/devicetree/msg51117.html Signed-off-by: Thor Thayer --- v2: Remove OCRAM declaration and reference prior patch. v3: No Change --- .../bindings/arm/altera/socfpga-l2-edac.txt | 15 +++++++++++++++ .../bindings/arm/altera/socfpga-ocram-edac.txt | 16 ++++++++++++++++ arch/arm/boot/dts/socfpga.dtsi | 15 ++++++++++++++- 3 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt new file mode 100644 index 0000000..35b19e3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt @@ -0,0 +1,15 @@ +Altera SoCFPGA L2 cache Error Detection and Correction [EDAC] + +Required Properties: +- compatible : Should be "altr,l2-edac" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. Note the rising edge type. + +Example: + + l2edac@ffd08140 { + compatible = "altr,l2-edac"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt new file mode 100644 index 0000000..31ab205 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt @@ -0,0 +1,16 @@ +Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC] + +OCRAM ECC Required Properties: +- compatible : Should be "altr,ocram-edac" +- reg : Address and size for ECC error interrupt clear registers. +- iram : phandle to On-Chip RAM definition. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. Note the rising edge type. + +Example: + ocramedac@ffd08144 { + compatible = "altr,ocram-edac"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6af96ed..32c63a3 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -618,8 +618,21 @@ interrupts = <0 39 4>; }; + l2edac@ffd08140 { + compatible = "altr,l2-edac"; + reg = <0xffd08140 0x4>; + interrupts = <0 36 1>, <0 37 1>; + }; + + ocramedac@ffd08144 { + compatible = "altr,ocram-edac"; + reg = <0xffd08144 0x4>; + iram = <&ocram>; + interrupts = <0 178 1>, <0 179 1>; + }; + L2: l2-cache@fffef000 { - compatible = "arm,pl310-cache"; + compatible = "arm,pl310-cache", "syscon"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; cache-unified;