From patchwork Mon Nov 3 15:04:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yogesh Tillu X-Patchwork-Id: 5217371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 748C1C11AC for ; Mon, 3 Nov 2014 15:11:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E1F72015D for ; Mon, 3 Nov 2014 15:11:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 57E662012B for ; Mon, 3 Nov 2014 15:11:16 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlJFq-0004qQ-Rl; Mon, 03 Nov 2014 15:09:14 +0000 Received: from mail-pa0-f54.google.com ([209.85.220.54]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlJFc-0004eB-EV for linux-arm-kernel@lists.infradead.org; Mon, 03 Nov 2014 15:09:01 +0000 Received: by mail-pa0-f54.google.com with SMTP id rd3so12220145pab.41 for ; Mon, 03 Nov 2014 07:08:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jeSXOjm6gpAM+Odx6mj7QoNKHA16tklWR/JrBg75Npo=; b=BLongJQ7S43ED6a1gAOkomRcvC4LfV6vEIVsYQUZONdOL21Vkv/JC4rCStktaFG6h+ 5g3yTCMkWBJESWhetgGWryUdapx8ydtdG8DEi2HNY7kaLVaPTsswnthPtZe43GLaxf0N 7vjTxWYE50DQB0Kf7ZpFEytg+QUIMtdoJXQo2et2mVUVaDhWvvP7q7E+2wZDT/YjN6Ta pfRNYapNSjaQ6I0GncIwO0ER0d0rnBO3iDwje5qPVBHAPXQElt+9BxJYs5LJ9xCqZkaL qIh3ZSUpC2gXqBILO1uczyZj9bEhO5EVBN35y1P9UNf6a3B2GhbxjgwbRdBGok68sA35 UGeA== X-Gm-Message-State: ALoCoQlYEBz7CSHFu3rA4Pdp7Xe/abeuKMOy/cMa6dU2dVXGDvaRSQJgXKXZkgkfr2woLeRo1r4F X-Received: by 10.70.2.65 with SMTP id 1mr42901098pds.13.1415027319552; Mon, 03 Nov 2014 07:08:39 -0800 (PST) Received: from yogesh-Dell-System-Vostro-3360.Airtel4Grouter.cpe ([14.140.2.178]) by mx.google.com with ESMTPSA id mp5sm17413005pbc.33.2014.11.03.07.08.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Nov 2014 07:08:38 -0800 (PST) From: Yogesh Tillu To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 3/5] Application: Added test for Direct access of perf counter from userspace using asm. Date: Mon, 3 Nov 2014 20:34:03 +0530 Message-Id: <1415027045-6573-4-git-send-email-yogesh.tillu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415027045-6573-1-git-send-email-yogesh.tillu@linaro.org> References: <1415027045-6573-1-git-send-email-yogesh.tillu@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141103_070900_540224_42F1B045 X-CRM114-Status: GOOD ( 16.96 ) X-Spam-Score: -0.7 (/) Cc: magnus.karlsson@avagotech.com, tillu.yogesh@gmail.com, Prasun.Kapoor@caviumnetworks.com, linux-perf-users@vger.kernel.org, Andrew.Pinski@caviumnetworks.com, mike.holmes@linaro.org, ola.liljedahl@linaro.org, Yogesh Tillu , linaro-networking@linaro.org, jean.pihet@linaro.org, arnd@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patchset contains Test application for accessing perf cycle counter from userspace using asm. Signed-off-by: Yogesh Tillu --- README.directaccess | 8 ++++ direct_access.c | 65 ++++++++++++++++++++++++++++ direct_access.h | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 190 insertions(+) create mode 100644 README.directaccess create mode 100644 direct_access.c create mode 100644 direct_access.h diff --git a/README.directaccess b/README.directaccess new file mode 100644 index 0000000..99e929c --- /dev/null +++ b/README.directaccess @@ -0,0 +1,8 @@ +To Cross-compile application: + ~/arm64-tc-14.06/bin/aarch64-linux-gnu-gcc -std=gnu99 -O3 direct_access.c + -o direct_access + +Run: +1) Insert kernel module to enable userspace access of perf cycle counter +2) $./direct_access 64 [ Pass same random number as with test + of perf_event_open ] diff --git a/direct_access.c b/direct_access.c new file mode 100644 index 0000000..7a9e9b2 --- /dev/null +++ b/direct_access.c @@ -0,0 +1,65 @@ +#include +#include +#include +#include "direct_access.h" +/* Simple loop body to keep things interested. Make sure it gets inlined. */ +static inline int +loop(int* __restrict__ a, int* __restrict__ b, int n) +{ + unsigned sum = 0; + for (int i = 0; i < n; ++i) + if(a[i] > b[i]) + sum += a[i] + 5; + return sum; +} + +int +main(int ac, char **av) +{ + uint32_t time_start = 0; + uint32_t time_end = 0; + int result=0; + int *a = NULL; + int *b = NULL; + int len = 0; + int sum = 0; + int i; + + if (ac != 2) return -1; + len = atoi(av[1]); + + a = malloc(len*sizeof(*a)); + b = malloc(len*sizeof(*b)); + + for (int i = 0; i < len; ++i) { + a[i] = i+128; + b[i] = i+64; + } +/* Open Counter */ + if(odph_perf_open_counter()!=0) + { + printf("Error in perf_open_counter\n"); + goto cleanup; + } + printf("\nbeginning busy loop for %s len=%d \n", av[0],len); +/* Read Counter with Busy loop */ + time_start = odph_perf_read_counter(); + sum = loop(a, b, len); + time_end = odph_perf_read_counter(); + printf("**********************************************************************\n"); + printf("Busyloop sum = %d\nTime delta Including Busyloop = %lu [clockcycle]\n", sum, time_end - time_start); + +/* Read Counter with profiling read_counter */ + time_start = odph_perf_read_counter(); + odph_perf_read_counter(); + time_end = odph_perf_read_counter(); + printf("\nTime delta Without Busyloop = %lu [clockcycle]\n", time_end - time_start); + printf("**********************************************************************\n"); + +/* Close Counter */ + odph_perf_close_counter(); + free(a); free(b); + return 0; +cleanup: + return -1; +} diff --git a/direct_access.h b/direct_access.h new file mode 100644 index 0000000..f7ac20b --- /dev/null +++ b/direct_access.h @@ -0,0 +1,117 @@ +/* Copyright (c) 2014, Linaro Limited + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +/** + * @file + * + * Performance Counter Direct access Header + */ + +#ifndef DIRECT_ACCESS_H_ +#define DIRECT_ACCESS_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#if __aarch64__ /**< Check for ArmV8 */ +#define ARMV8_PMCNTENSET_EL0_ENABLE (1<<31) /**< Enable Perf count reg */ +#endif + +/** + * Open Performance counter + * + * @note api to enable performance counters in system, this function does + * enable sequence for respective arm versions + * + * @param void + * + * @return 0 if open successfully, otherwise -1 + */ +static inline int odph_perf_open_counter(void) +{ + +#if __aarch64__ +/* Performance Monitors Count Enable Set register bit 31:0 disable, 1 enable */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (ARMV8_PMCNTENSET_EL0_ENABLE)); + return 0; +#elif defined(__ARM_ARCH_7A__) + return 0; +#else + #error Unsupported Architecture + return -1; +#endif +} + +/** + * Read Performance counter + * + * @note api to read performance cycle counters in system + * + * @param void + * + * @return cycle counter value if read successfully, otherwise -1 + */ +static inline uint64_t +odph_perf_read_counter(void) +{ +uint64_t ret = 0; +#if defined __aarch64__ + asm volatile("mrs %0, pmccntr_el0" : "=r" (ret)); + return ret; +#elif defined(__ARM_ARCH_7A__) + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(ret)); + return ret; +#else + #error Unsupported architecture/compiler! + return -1; +#endif +} + +/** + * Write Performance counter + * + * @note api to write value to Performance counter, + * NA for now + * + * @param void + * + * @return 0 if written successfully, otherwise -1 + */ +static inline int odph_perf_write_counter(void) +{ +/* Stub */ +} + +/** + * Close Performance counter + * + * @note api to perform close sequnce for cycle counters in system + * + * @param void + * + * @return 0 if close successfully, otherwise -1 + */ +static inline int odph_perf_close_counter(void) +{ +#if defined __aarch64__ + /* Performance Monitors Count Enable Set register bit 31:0 disable, 1 enable */ + asm volatile("msr pmcntenset_el0, %0" : : "r" (0<<31)); + /* Note above statement does not really clearing register...refer to doc */ + return 0; +#elif defined(__ARM_ARCH_7A__) + return 0; +#else + #error Unsupported architecture/compiler! + return -1; +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* DIRECT_ACCESS_H_ */