| Message ID | 1415203287-21517-7-git-send-email-boris.brezillon@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Boris, 2014-11-05 17:01 GMT+01:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > --- > .../bindings/memory-controllers/atmel-ebi.txt | 153 +++++++++++++++++++++ > 1 file changed, 153 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > new file mode 100644 > index 0000000..dc2c34f > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > @@ -0,0 +1,153 @@ > +* Device tree bindings for Atmel EBI > + > +The External Bus Interface (EBI) controller is a bus where you can connect > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > +The EBI provides a glue-less interface to asynchronous memories though the SMC > +(Static Memory Controller). > +Synchronous memories (and some asynchronous memories like NANDs) can be > +attached to specialized controllers which are responsible for configuring the > +bus appropriately according to the connected device. > +In the other hand, the bus interface can be automated for simple asynchronous > +devices. > + > +Required properties: > + > +- compatible: "atmel,at91sam9260-ebi" > + "atmel,at91sam9261-ebi" > + "atmel,at91sam9263-ebi0" > + "atmel,at91sam9263-ebi1" > + "atmel,at91sam9g45-ebi" > + "atmel,at91sam9x5-ebi" > + "atmel,sama5d3-ebi" > + > +- reg: Contains offset/length value for EBI memory mapping. > + This property might contain several entries if the EBI > + memory range is not contiguous > + > +- #address-cells: Must be 2. > + The first cell encodes the CS. > + The second cell encode the offset into the CS memory > + range. > + > +- #size-cells: Must be set to 1. > + > +- ranges: Encodes CS to memory region association. > + > +- clocks: Clock feeding the EBI controller. > + See clock-bindings.txt > + > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > +There might be board specific devices like FPGAs. > +You'll define you device requirements in these child nodes. > + > +Required child cs node properties: > + > +- #address-cells: Must be 2. > + > +- #size-cells: Must be 1. > + > +- ranges: Empty property indicating that child nodes can inherit > + memory layout. > + > +Optional child cs node properties: > +- atmel,generic-dev boolean property specifying if the device is > + a generic device. > + The following properties are only parsed if > + this property is present. > + Specialized devices are attached to specialized > + controllers which should configure the bus > + appropriately. What do you mean by specialized devices ? Can you give an example ? > + > +- atmel,bus-width: width of the asynchronous device's data bus > + 8, 16 or 32. > + 8 if not present. > + > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > + "select" if not present. > + > +- atmel,read-mode "nrd" or "ncs". > + "ncs" is not present. > + > +- atmel,write-mode "nwe" or "ncs". > + "ncs" is not present. > + > +- atmel,exnw-mode "disabled", "frozen" or "ready". > + "disabled" if not present. > + > +- atmel,page-mode enable page mode if present. The provided value > + defines the page size (supported values: 4, 8, > + 16 and 32). > + > +Optional device timings expressed in nanoseconds (if the property is not > +present 0 is assumed): > + > +- atmel,ncs-rd-setup-ns > +- atmel,nrd-setup-ns > +- atmel,ncs-wr-setup-ns > +- atmel,nwe-setup-ns > +- atmel,ncs-rd-pulse-ns > +- atmel,nrd-pulse-ns > +- atmel,ncs-wr-pulse-ns > +- atmel,nwe-pulse-ns > +- atmel,nwe-cycle-ns > +- atmel,nrd-cycle-ns > +- atmel,tdf-ns > + > +- atmel,tdf-optimized data float optimized mode. If present the data > + float time is optimized depending on the next > + device being accessed (next device setup > + time is substracted to the current devive data > + float time). > + > + > + > +Example: > + > + ebi: ebi@10000000 { > + compatible = "atmel,sama5d3-ebi", "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; > + atmel,smc = <&hsmc>; > + atmel,matrix = <&matrix>; > + reg = <0x10000000 0x10000000 > + 0x40000000 0x30000000>; > + ranges = <0x0 0x0 0x10000000 0x10000000 > + 0x1 0x0 0x40000000 0x10000000 > + 0x2 0x0 0x50000000 0x10000000 > + 0x3 0x0 0x60000000 0x10000000>; > + clocks = <&mck>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ebi_addr>; > + > + cs@0 { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + atmel,generic-dev; > + atmel,read-mode = "nrd"; > + atmel,write-mode = "nwe"; > + atmel,bus-width = <16>; > + atmel,ncs-rd-setup-ns = <0>; > + atmel,ncs-wr-setup-ns = <0>; > + atmel,nwe-setup-ns = <8>; > + atmel,nrd-setup-ns = <16>; > + atmel,ncs-rd-pulse-ns = <84>; > + atmel,ncs-wr-pulse-ns = <84>; > + atmel,nrd-pulse-ns = <76>; > + atmel,nwe-pulse-ns = <76>; > + atmel,nrd-cycle-ns = <107>; > + atmel,nwe-cycle-ns = <84>; > + atmel,tdf-ns = <16>; > + > + nor: flash@0,0 { > + compatible = "cfi-flash"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0 0x0 0x1000000>; > + bank-width = <2>; > + }; > + }; > + }; > + > -- > 1.9.1 >
On Wed, 5 Nov 2014 17:22:57 +0100 Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > Hi Boris, > > 2014-11-05 17:01 GMT+01:00 Boris Brezillon <boris.brezillon@free-electrons.com>: > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > --- > > .../bindings/memory-controllers/atmel-ebi.txt | 153 +++++++++++++++++++++ > > 1 file changed, 153 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > > > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > > new file mode 100644 > > index 0000000..dc2c34f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > > @@ -0,0 +1,153 @@ > > +* Device tree bindings for Atmel EBI > > + > > +The External Bus Interface (EBI) controller is a bus where you can connect > > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > > +The EBI provides a glue-less interface to asynchronous memories though the SMC > > +(Static Memory Controller). > > +Synchronous memories (and some asynchronous memories like NANDs) can be > > +attached to specialized controllers which are responsible for configuring the > > +bus appropriately according to the connected device. > > +In the other hand, the bus interface can be automated for simple asynchronous > > +devices. [...] > > + > > +Optional child cs node properties: > > +- atmel,generic-dev boolean property specifying if the device is > > + a generic device. > > + The following properties are only parsed if > > + this property is present. > > + Specialized devices are attached to specialized > > + controllers which should configure the bus > > + appropriately. > > What do you mean by specialized devices ? Can you give an example ? The ones I have in mind are NAND chips: the NAND controller can automatically discover the required timings and configure the SMC accordingly. In that case there's no need to specify timings in the DT, because they will/should be dynalically configured by the NAND controller driver. But more generally, the datasheet describe 2 modes for some CS ports: 1) the generic mode, which bind the device to the generic SMC engine 2) the specialized mode which binds it to a specific HW block This mode can be configured in CCFG_EBICSA, and the specialized mode supported by each CS depends on each SoC. For example, for the at91sam9x5: CS1 => DDR2SDR controller CS3 => NAND Flash Controller/Logic
We probabyl should start making sure we have a commit log for every patches ;) On 05/11/2014 at 17:01:22 +0100, Boris Brezillon wrote : > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > +There might be board specific devices like FPGAs. > +You'll define you device requirements in these child nodes. your
On Wed, Nov 5, 2014 at 10:01 AM, Boris Brezillon <boris.brezillon@free-electrons.com> wrote: > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Perhaps some commit msg? While this binding seems mostly okay to me, this is the 2nd memory controller binding I've looked at in the last day [1]. There are probably some others already as well. This makes me think we need a generic binding here. At least the node structure and how we define chip selects should be common. While I like timing information in time units over magic register values in the Tegra binding, the reality is converting timing info to register values is generally very hard to get both correct and optimal. In the end, you probably need to hand tweak the register settings anyway. So I'm hesitant to say it must be done 1 way here. Rob [1] http://lwn.net/Articles/618466/ > --- > .../bindings/memory-controllers/atmel-ebi.txt | 153 +++++++++++++++++++++ > 1 file changed, 153 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > new file mode 100644 > index 0000000..dc2c34f > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt > @@ -0,0 +1,153 @@ > +* Device tree bindings for Atmel EBI > + > +The External Bus Interface (EBI) controller is a bus where you can connect > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). > +The EBI provides a glue-less interface to asynchronous memories though the SMC > +(Static Memory Controller). > +Synchronous memories (and some asynchronous memories like NANDs) can be > +attached to specialized controllers which are responsible for configuring the > +bus appropriately according to the connected device. > +In the other hand, the bus interface can be automated for simple asynchronous > +devices. > + > +Required properties: > + > +- compatible: "atmel,at91sam9260-ebi" > + "atmel,at91sam9261-ebi" > + "atmel,at91sam9263-ebi0" > + "atmel,at91sam9263-ebi1" > + "atmel,at91sam9g45-ebi" > + "atmel,at91sam9x5-ebi" > + "atmel,sama5d3-ebi" > + > +- reg: Contains offset/length value for EBI memory mapping. > + This property might contain several entries if the EBI > + memory range is not contiguous > + > +- #address-cells: Must be 2. > + The first cell encodes the CS. > + The second cell encode the offset into the CS memory > + range. > + > +- #size-cells: Must be set to 1. > + > +- ranges: Encodes CS to memory region association. > + > +- clocks: Clock feeding the EBI controller. > + See clock-bindings.txt > + > +Child chip-select (cs) nodes contain the memory devices nodes connected to > +such as NOR (e.g. cfi-flash) and NAND. > +There might be board specific devices like FPGAs. > +You'll define you device requirements in these child nodes. > + > +Required child cs node properties: > + > +- #address-cells: Must be 2. > + > +- #size-cells: Must be 1. > + > +- ranges: Empty property indicating that child nodes can inherit > + memory layout. > + > +Optional child cs node properties: > +- atmel,generic-dev boolean property specifying if the device is > + a generic device. > + The following properties are only parsed if > + this property is present. > + Specialized devices are attached to specialized > + controllers which should configure the bus > + appropriately. > + > +- atmel,bus-width: width of the asynchronous device's data bus > + 8, 16 or 32. > + 8 if not present. > + > +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). > + "select" if not present. > + > +- atmel,read-mode "nrd" or "ncs". > + "ncs" is not present. > + > +- atmel,write-mode "nwe" or "ncs". > + "ncs" is not present. > + > +- atmel,exnw-mode "disabled", "frozen" or "ready". > + "disabled" if not present. > + > +- atmel,page-mode enable page mode if present. The provided value > + defines the page size (supported values: 4, 8, > + 16 and 32). > + > +Optional device timings expressed in nanoseconds (if the property is not > +present 0 is assumed): > + > +- atmel,ncs-rd-setup-ns > +- atmel,nrd-setup-ns > +- atmel,ncs-wr-setup-ns > +- atmel,nwe-setup-ns > +- atmel,ncs-rd-pulse-ns > +- atmel,nrd-pulse-ns > +- atmel,ncs-wr-pulse-ns > +- atmel,nwe-pulse-ns > +- atmel,nwe-cycle-ns > +- atmel,nrd-cycle-ns > +- atmel,tdf-ns > + > +- atmel,tdf-optimized data float optimized mode. If present the data > + float time is optimized depending on the next > + device being accessed (next device setup > + time is substracted to the current devive data > + float time). > + > + > + > +Example: > + > + ebi: ebi@10000000 { > + compatible = "atmel,sama5d3-ebi", "simple-bus"; > + #address-cells = <2>; > + #size-cells = <1>; > + atmel,smc = <&hsmc>; > + atmel,matrix = <&matrix>; > + reg = <0x10000000 0x10000000 > + 0x40000000 0x30000000>; > + ranges = <0x0 0x0 0x10000000 0x10000000 > + 0x1 0x0 0x40000000 0x10000000 > + 0x2 0x0 0x50000000 0x10000000 > + 0x3 0x0 0x60000000 0x10000000>; > + clocks = <&mck>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ebi_addr>; > + > + cs@0 { > + #address-cells = <2>; > + #size-cells = <1>; > + ranges; > + atmel,generic-dev; > + atmel,read-mode = "nrd"; > + atmel,write-mode = "nwe"; > + atmel,bus-width = <16>; > + atmel,ncs-rd-setup-ns = <0>; > + atmel,ncs-wr-setup-ns = <0>; > + atmel,nwe-setup-ns = <8>; > + atmel,nrd-setup-ns = <16>; > + atmel,ncs-rd-pulse-ns = <84>; > + atmel,ncs-wr-pulse-ns = <84>; > + atmel,nrd-pulse-ns = <76>; > + atmel,nwe-pulse-ns = <76>; > + atmel,nrd-cycle-ns = <107>; > + atmel,nwe-cycle-ns = <84>; > + atmel,tdf-ns = <16>; > + > + nor: flash@0,0 { > + compatible = "cfi-flash"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0 0x0 0x1000000>; > + bank-width = <2>; > + }; > + }; > + }; > + > -- > 1.9.1 >
On Fri, 7 Nov 2014 09:21:39 -0600 Rob Herring <robherring2@gmail.com> wrote: > On Wed, Nov 5, 2014 at 10:01 AM, Boris Brezillon > <boris.brezillon@free-electrons.com> wrote: > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > > Perhaps some commit msg? Yes, I was just lazy and though this series would make another round anyway :-). I'll add a commit log to all my commits... > > While this binding seems mostly okay to me, this is the 2nd memory > controller binding I've looked at in the last day [1]. There are > probably some others already as well. This makes me think we need a > generic binding here. At least the node structure and how we define > chip selects should be common. Sure. Any suggestion ? BTW, I don't use any specific property to define the chip select associated to a device, because it's already encoded in the reg property. TI AEMIF binding define an ti,cs-chipselect property, is there any reason for doing that ? Moreover, IMHO it would even make sense to have some sort of framework/helper functions for those kind of interfaces to external memories, but this is another story :-). > > While I like timing information in time units over magic register > values in the Tegra binding, the reality is converting timing info to > register values is generally very hard to get both correct and > optimal. In the end, you probably need to hand tweak the register > settings anyway. So I'm hesitant to say it must be done 1 way here. Well, I'm not a big fan of timings expressed in clock cycles, cause this implies changing your DT when you tweak your master/bus clk. Expressing those timings in nano or pico seconds let the driver figure out what's the best value according to the current source clk rate. Regards, Boris
On 7 November 2014 16:49, Boris Brezillon <boris.brezillon@free-electrons.com> wrote: > On Fri, 7 Nov 2014 09:21:39 -0600 > Rob Herring <robherring2@gmail.com> wrote: > >> On Wed, Nov 5, 2014 at 10:01 AM, Boris Brezillon >> <boris.brezillon@free-electrons.com> wrote: >> > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> >> >> Perhaps some commit msg? > > Yes, I was just lazy and though this series would make another round > anyway :-). > > I'll add a commit log to all my commits... > >> >> While this binding seems mostly okay to me, this is the 2nd memory >> controller binding I've looked at in the last day [1]. There are >> probably some others already as well. This makes me think we need a >> generic binding here. At least the node structure and how we define >> chip selects should be common. > > Sure. > Any suggestion ? I unfortunately cannot see much benefit to a generic binding, but maybe that's because the one in T124 is a bit special? I'm very interested in hearing proposals though. Thanks, Tomeu
diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt new file mode 100644 index 0000000..dc2c34f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt @@ -0,0 +1,153 @@ +* Device tree bindings for Atmel EBI + +The External Bus Interface (EBI) controller is a bus where you can connect +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). +The EBI provides a glue-less interface to asynchronous memories though the SMC +(Static Memory Controller). +Synchronous memories (and some asynchronous memories like NANDs) can be +attached to specialized controllers which are responsible for configuring the +bus appropriately according to the connected device. +In the other hand, the bus interface can be automated for simple asynchronous +devices. + +Required properties: + +- compatible: "atmel,at91sam9260-ebi" + "atmel,at91sam9261-ebi" + "atmel,at91sam9263-ebi0" + "atmel,at91sam9263-ebi1" + "atmel,at91sam9g45-ebi" + "atmel,at91sam9x5-ebi" + "atmel,sama5d3-ebi" + +- reg: Contains offset/length value for EBI memory mapping. + This property might contain several entries if the EBI + memory range is not contiguous + +- #address-cells: Must be 2. + The first cell encodes the CS. + The second cell encode the offset into the CS memory + range. + +- #size-cells: Must be set to 1. + +- ranges: Encodes CS to memory region association. + +- clocks: Clock feeding the EBI controller. + See clock-bindings.txt + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND. +There might be board specific devices like FPGAs. +You'll define you device requirements in these child nodes. + +Required child cs node properties: + +- #address-cells: Must be 2. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +Optional child cs node properties: +- atmel,generic-dev boolean property specifying if the device is + a generic device. + The following properties are only parsed if + this property is present. + Specialized devices are attached to specialized + controllers which should configure the bus + appropriately. + +- atmel,bus-width: width of the asynchronous device's data bus + 8, 16 or 32. + 8 if not present. + +- atmel,byte-access-type "write" or "select" (see Atmel datasheet). + "select" if not present. + +- atmel,read-mode "nrd" or "ncs". + "ncs" is not present. + +- atmel,write-mode "nwe" or "ncs". + "ncs" is not present. + +- atmel,exnw-mode "disabled", "frozen" or "ready". + "disabled" if not present. + +- atmel,page-mode enable page mode if present. The provided value + defines the page size (supported values: 4, 8, + 16 and 32). + +Optional device timings expressed in nanoseconds (if the property is not +present 0 is assumed): + +- atmel,ncs-rd-setup-ns +- atmel,nrd-setup-ns +- atmel,ncs-wr-setup-ns +- atmel,nwe-setup-ns +- atmel,ncs-rd-pulse-ns +- atmel,nrd-pulse-ns +- atmel,ncs-wr-pulse-ns +- atmel,nwe-pulse-ns +- atmel,nwe-cycle-ns +- atmel,nrd-cycle-ns +- atmel,tdf-ns + +- atmel,tdf-optimized data float optimized mode. If present the data + float time is optimized depending on the next + device being accessed (next device setup + time is substracted to the current devive data + float time). + + + +Example: + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi", "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x40000000 0x10000000 + 0x2 0x0 0x50000000 0x10000000 + 0x3 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr>; + + cs@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges; + atmel,generic-dev; + atmel,read-mode = "nrd"; + atmel,write-mode = "nwe"; + atmel,bus-width = <16>; + atmel,ncs-rd-setup-ns = <0>; + atmel,ncs-wr-setup-ns = <0>; + atmel,nwe-setup-ns = <8>; + atmel,nrd-setup-ns = <16>; + atmel,ncs-rd-pulse-ns = <84>; + atmel,ncs-wr-pulse-ns = <84>; + atmel,nrd-pulse-ns = <76>; + atmel,nwe-pulse-ns = <76>; + atmel,nrd-cycle-ns = <107>; + atmel,nwe-cycle-ns = <84>; + atmel,tdf-ns = <16>; + + nor: flash@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x1000000>; + bank-width = <2>; + }; + }; + }; +
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- .../bindings/memory-controllers/atmel-ebi.txt | 153 +++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt