From patchwork Fri Nov 7 16:25:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 5254261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F2F68C11AC for ; Fri, 7 Nov 2014 16:29:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F8D02012E for ; Fri, 7 Nov 2014 16:29:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1793120145 for ; Fri, 7 Nov 2014 16:29:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XmmO7-0008Rj-MC; Fri, 07 Nov 2014 16:27:51 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XmmNT-0007rg-BC for linux-arm-kernel@lists.infradead.org; Fri, 07 Nov 2014 16:27:12 +0000 Received: from leverpostej.cambridge.arm.com (leverpostej.cambridge.arm.com [10.1.205.151]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id sA7GPwwv014702; Fri, 7 Nov 2014 16:26:50 GMT From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/11] arm: perf: document PMU affinity binding Date: Fri, 7 Nov 2014 16:25:32 +0000 Message-Id: <1415377536-12841-8-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415377536-12841-1-git-send-email-mark.rutland@arm.com> References: <1415377536-12841-1-git-send-email-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141107_082711_772756_1A7D6C0C X-CRM114-Status: GOOD ( 10.07 ) X-Spam-Score: -5.6 (-----) Cc: Mark Rutland , will.deacon@arm.com, linux-kernel@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To describe the various ways CPU PMU interrupts might be wired up, we can refer to the topology information in the device tree. This patch adds a new property to the PMU binding, interrupts-affinity, which describes the relationship between CPUs and interrupts. This information is necessary to handle systems with heterogeneous PMU implementations (e.g. big.LITTLE). Documentation is added describing the use of said property. Signed-off-by: Mark Rutland --- Documentation/devicetree/bindings/arm/pmu.txt | 104 +++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index 75ef91d..23a0675 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt @@ -24,12 +24,114 @@ Required properties: Optional properties: +- interrupts-affinity : A list of phandles to topology nodes (see topology.txt) describing + the set of CPUs associated with the interrupt at the same index. - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd events. -Example: +Example 1 (A single CPU): pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <100 101>; }; + +Example 2 (Multiple clusters with single interrupts): + +cpus { + #address-cells = <1>; + #size-cells = <1>; + + CPU0: cpu@0 { + reg = <0x0>; + compatible = "arm,cortex-a15-pmu"; + }; + + CPU1: cpu@1 { + reg = <0x1>; + compatible = "arm,cotex-a15-pmu"; + }; + + CPU100: cpu@100 { + reg = <0x100>; + compatible = "arm,cortex-a7-pmu"; + }; + + cpu-map { + cluster0 { + CORE_0_0: core0 { + cpu = <&CPU0>; + }; + CORE_0_1: core1 { + cpu = <&CPU1>; + }; + }; + cluster1 { + CORE_1_0: core0 { + cpu = <&CPU100>; + }; + }; + }; +}; + +pmu_a15 { + compatible = "arm,cortex-a15-pmu"; + interrupts = <100>, <101>; + interrupts-affinity = <&CORE0>, <&CORE1>; +}; + +pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <105>; + interrupts-affinity = <&CORE_1_0>; +}; + +Example 3 (Multiple clusters with per-cpu interrupts): + +cpus { + #address-cells = <1>; + #size-cells = <1>; + + CPU0: cpu@0 { + reg = <0x0>; + compatible = "arm,cortex-a15-pmu"; + }; + + CPU1: cpu@1 { + reg = <0x1>; + compatible = "arm,cotex-a15-pmu"; + }; + + CPU100: cpu@100 { + reg = <0x100>; + compatible = "arm,cortex-a7-pmu"; + }; + + cpu-map { + CLUSTER0: cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + CLUSTER1: cluster1 { + core0 { + cpu = <&CPU100>; + }; + }; + }; +}; + +pmu_a15 { + compatible = "arm,cortex-a15-pmu"; + interrupts = <100>; + interrupts-affinity = <&CLUSTER0>; +}; + +pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <105>; + interrupts-affinity = <&CLUSTER1>; +};