From patchwork Fri Nov 14 16:25:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 5308421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3424CC11AC for ; Fri, 14 Nov 2014 16:29:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 459E020149 for ; Fri, 14 Nov 2014 16:29:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 51DF820176 for ; Fri, 14 Nov 2014 16:29:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XpJiQ-0005HG-GC; Fri, 14 Nov 2014 16:27:18 +0000 Received: from mail-wi0-x22e.google.com ([2a00:1450:400c:c05::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XpJhx-00050v-Qw for linux-arm-kernel@lists.infradead.org; Fri, 14 Nov 2014 16:26:50 +0000 Received: by mail-wi0-f174.google.com with SMTP id h11so3230720wiw.7 for ; Fri, 14 Nov 2014 08:26:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bo/oTOFoHjNPdky7WNau/Mx8ZHFAjyXQC2DzduLKA2c=; b=ocY/q9vV94pFuAKCUoKXMiOdLpZ3DvRannQM52fzxHU9gYrxoJ7rtoiKQmAJfamnem yek4FDLWj8ZZ61NRZkMbEBqEUDgDOATBH5lTQTaT3Fflps4Axjgj9LzW5obMuM2gtNx0 GpR43J8sNfNjI7Lgc3gD2S9UKlapxEei1yTmyLHIoUhMFhyRSZT+gNphdTIfjTIHFv8f 5Kjo3ByAR1Ff/dvJc/FTIicQFm+xw1vNFdVNZJxepyjEtFmcwSIdAaax8qyeyxghyh4l hwuxDsZ/GTeUe/VlSRXLTPUSL/9rJaRsxzWvm8IOXX8O4By061tA72dVSIX2APdnGziK 9NAw== X-Received: by 10.194.185.167 with SMTP id fd7mr15743232wjc.108.1415982384225; Fri, 14 Nov 2014 08:26:24 -0800 (PST) Received: from localhost.localdomain (host38-130-dynamic.51-79-r.retail.telecomitalia.it. [79.51.130.38]) by mx.google.com with ESMTPSA id 10sm40218990wjs.21.2014.11.14.08.26.22 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 14 Nov 2014 08:26:23 -0800 (PST) From: Carlo Caione To: linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@arm.linux.org.uk, maxime.ripard@free-electrons.com, b.galvani@gmail.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, arnd@arndb.de, eric.hankinson@leandogsoftware.com Subject: [PATCH RESEND 2/3] ARM: Meson6: Add SMP support for Amlogic Meson6 Date: Fri, 14 Nov 2014 17:25:52 +0100 Message-Id: <1415982353-9293-3-git-send-email-carlo@caione.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415982353-9293-1-git-send-email-carlo@caione.org> References: <1415982353-9293-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141114_082650_063706_402048FB X-CRM114-Status: GOOD ( 14.13 ) X-Spam-Score: -0.7 (/) Cc: Carlo Caione X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_LOW, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Amlogic Meson6 is a dual core Cortex-A9. This patch adds the logic to boot up the second CPU. Signed-off-by: Carlo Caione --- arch/arm/mach-meson/Kconfig | 1 + arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/headsmp.S | 7 ++++ arch/arm/mach-meson/platsmp.c | 80 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 arch/arm/mach-meson/headsmp.S create mode 100644 arch/arm/mach-meson/platsmp.c diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 2c1154e..4e96de4 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -2,6 +2,7 @@ menuconfig ARCH_MESON bool "Amlogic Meson SoCs" if ARCH_MULTI_V7 select GENERIC_IRQ_CHIP select ARM_GIC + select HAVE_ARM_SCU if SMP if ARCH_MESON diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 9d7380e..4691966 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_ARCH_MESON) += meson.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-meson/headsmp.S b/arch/arm/mach-meson/headsmp.S new file mode 100644 index 0000000..3347d88 --- /dev/null +++ b/arch/arm/mach-meson/headsmp.S @@ -0,0 +1,7 @@ +#include +#include + +ENTRY(meson_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(meson_secondary_startup) diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c new file mode 100644 index 0000000..3d4d0cd --- /dev/null +++ b/arch/arm/mach-meson/platsmp.c @@ -0,0 +1,80 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MESON_CPU_CONTROL_REG 0x0 +#define MESON_CPU1_CONTROL_ADDR_REG 0x4 + +#define MESON_CPU_CONTROL_ID(cpu) ((1 << (cpu)) | 1) + +static void __iomem *cpucfg_membase; +static void __iomem *scu_membase; + +static DEFINE_SPINLOCK(cpu_lock); + +extern void meson_secondary_startup(void); + +static void __init meson6_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!node) { + pr_err("Missing Meson6 SCU node\n"); + return; + } + + scu_membase = of_iomap(node, 0); + if (!scu_membase) { + pr_err("Couln't map Meson6 SCU registers\n"); + return; + } + + node = of_find_compatible_node(NULL, NULL, "amlogic,meson6-cpuconfig"); + if (!node) { + pr_err("Missing Meson6 CPU config node\n"); + return; + } + + cpucfg_membase = of_iomap(node, 0); + if (!cpucfg_membase) { + pr_err("Couldn't map Meson6 CPU config registers\n"); + return; + } + + scu_enable(scu_membase); +} + +static int meson6_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (!cpucfg_membase) + return -EFAULT; + + spin_lock(&cpu_lock); + + writel(virt_to_phys(meson_secondary_startup), cpucfg_membase + + MESON_CPU1_CONTROL_ADDR_REG); + writel(MESON_CPU_CONTROL_ID(cpu), cpucfg_membase + + MESON_CPU_CONTROL_REG); + + smp_wmb(); + + dsb_sev(); + + spin_unlock(&cpu_lock); + + return 0; +} + +static struct smp_operations meson6_smp_ops __initdata = { + .smp_prepare_cpus = meson6_smp_prepare_cpus, + .smp_boot_secondary = meson6_smp_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(meson6_smp, "amlogic,meson6-smp", &meson6_smp_ops);