From patchwork Mon Nov 17 09:50:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Caesar X-Patchwork-Id: 5317101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6A6669F1E1 for ; Mon, 17 Nov 2014 09:55:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7E96D2015E for ; Mon, 17 Nov 2014 09:55:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40D2E2012B for ; Mon, 17 Nov 2014 09:55:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XqJ0C-00044n-MF; Mon, 17 Nov 2014 09:53:44 +0000 Received: from regular1.263xmail.com ([211.150.99.133]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XqIzP-0002iO-GU; Mon, 17 Nov 2014 09:52:56 +0000 Received: from wxt?rock-chips.com (unknown [192.168.167.130]) by regular1.263xmail.com (Postfix) with SMTP id 970E072F8; Mon, 17 Nov 2014 17:52:29 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 95D6C440; Mon, 17 Nov 2014 17:52:25 +0800 (CST) X-RL-SENDER: wxt@rock-chips.com X-FST-TO: linus.walleij@linaro.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: wxt@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wxt@rock-chips.com X-DNS-TYPE: 0 Received: from localhost (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 14188KD2796; Mon, 17 Nov 2014 17:52:28 +0800 (CST) From: Caesar Wang To: linus.walleij@linaro.org, linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Russell King Subject: [PATCH v12 3/3] ARM: dts: add rk3288 power-domain node Date: Mon, 17 Nov 2014 17:50:41 +0800 Message-Id: <1416217842-4716-4-git-send-email-caesar.wang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1416217842-4716-1-git-send-email-caesar.wang@rock-chips.com> References: <1416217842-4716-1-git-send-email-caesar.wang@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141117_015255_901761_739CD2A3 X-CRM114-Status: UNSURE ( 8.49 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: Mark Rutland , Ulf Hansson , Randy Dunlap , linux-doc@vger.kernel.org, djkurtz@chromium.org, dianders@chromium.org, caesar.wang@rock-chips.com, xxm@rock-chips.com, chris.zhong@rock-chips.com, linux-rockchip@lists.infradead.org, Grant Likely , Jack Dai , devicetree@vger.kernel.org, chm@rock-chips.com, Pawel Moll , Ian Campbell , "jinkun.hong" , Rob Herring , Dmitry Torokhov , linux-kernel@vger.kernel.org, fzf@rock-chips.com, Kumar Gala , cf@rock-chips.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the needed clocks into power-controller. why need we do so that? Firstly, we always be needed turn off clocks to save power when the system enter suspend.So we need to enumerate the clocks are needed to switch power doamin no and off. Secondly, Rk3288 reset circuit should be syncchronous reset and then sync revoked.so we need to enable clocks of all devices. Signed-off-by: Jack Dai Signed-off-by: jinkun.hong Signed-off-by: Caesar Wang --- Changes in v12: - Remove essential clocks from rk3288 PD_VIO domain, Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain transition. As a result we either fail to suspend or resume the system. Changes in v11: None Changes in v10: - fix missing the #include - remove the notes Changes in v9: - add decription for power-doamin node Changes in v8: - DTS go back to v2 Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - Decomposition power-controller, changed to multiple controller (gpu-power-controller, hevc-power-controller) Changes in v2: - make pd_vio clocks all one entry per line and alphabetize. - power: power-controller move back to pinctrl: pinctrl. arch/arm/boot/dts/rk3288.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cb18bb4..d9cd8c0 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -989,4 +990,62 @@ }; }; }; + + power: power-controller { + compatible = "rockchip,rk3288-power-controller"; + #power-domain-cells = <1>; + rockchip,pmu = <&pmu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu { + reg = ; + clocks = <&cru ACLK_GPU>; + }; + + pd_hevc { + reg = ; + clocks = <&cru ACLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>, + <&cru HCLK_HEVC>; + }; + + pd_vio { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_RGA>, + <&cru ACLK_VIP>, + <&cru ACLK_VOP0>, + <&cru ACLK_VOP1>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP0>, + <&cru HCLK_VOP1>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_LVDS_PHY>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_HDMI_CEC>, + <&cru SCLK_HDMI_HDCP>, + <&cru SCLK_ISP_JPE>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>; + }; + + pd_video { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + }; + }; };