From patchwork Thu Nov 20 11:42:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5347591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0072B9FD77 for ; Thu, 20 Nov 2014 11:45:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1FAA0201BB for ; Thu, 20 Nov 2014 11:45:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7EF69201FA for ; Thu, 20 Nov 2014 11:45:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrQ8k-0004QW-CV; Thu, 20 Nov 2014 11:43:10 +0000 Received: from mail-wg0-f53.google.com ([74.125.82.53]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrQ8h-0004PL-9g for linux-arm-kernel@lists.infradead.org; Thu, 20 Nov 2014 11:43:08 +0000 Received: by mail-wg0-f53.google.com with SMTP id l18so3467944wgh.12 for ; Thu, 20 Nov 2014 03:42:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=FdeCrSD4AZc/cMTMELh+KqN+coubyfsE2UbNJNiBq0A=; b=fyxICdo8n7sOQX4y26/iBhuv5IB4x0KZlMRDfAD3WaQkhfjB64JZw0+uVe7TaOTRSv mQrZUPgH8qurYd+RN4fEhR9tKWvT4qYipvkUR7yGmFG2janMEPpmSiKQAr481wxzh+ki 9mwyCQBCG3X0kscR4nbBbXxrJWjhxwEJy5foxz42rKEtBSB+YVjcTC5dqm5Nz6ki+8yY 99zb6zqx5I47jL0KyUwXwWQ9LukBmA7RL+lzlOE/cZSQxy+zd5E1K/b0RXOAtaxZjrIF iLMIxQ9G7uYaDvdfTWJ279TqLcZkfoACA4nBrtMxakq2zEXBbEFa4hTZBqy6MGNtkc35 s/Ug== X-Gm-Message-State: ALoCoQmW+zBj3ELIW0jzWQVp4LJGOLlMhx5jSSvlOSAMq1ZMXN480C0QuzkDp6htzZSifrtksCdl X-Received: by 10.180.103.225 with SMTP id fz1mr14995130wib.38.1416483764879; Thu, 20 Nov 2014 03:42:44 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id vm8sm3025563wjc.6.2014.11.20.03.42.42 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Nov 2014 03:42:43 -0800 (PST) From: Daniel Thompson To: Shawn Guo , Sascha Hauer Subject: [RFC PATCH] arm: imx: Workaround i.MX6 PMU interrupts muxed to one SPI Date: Thu, 20 Nov 2014 11:42:37 +0000 Message-Id: <1416483757-24165-1-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141120_034307_571120_5276A0F6 X-CRM114-Status: GOOD ( 17.16 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , Peter Zijlstra , patches@linaro.org, Will Deacon , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Ingo Molnar , Paul Mackerras , John Stultz , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP All PMU interrupts on multi-core i.MX6 devices are muxed onto a single SPI. Should the PMU of any core except 0 (the default affinity for the interrupt) trigger the interrupt then it cannot be serviced and, eventually, the spurious irq detection will forcefully disable the interrupt. This can be worked around by getting the interrupt handler to change its own affinity if it cannot figure out why it has been triggered. This patch adds logic to rotate the affinity to i.MX6. Signed-off-by: Daniel Thompson --- Notes: This patch adopts the approach used on the u8500 (db8500_pmu_handler) but the logic has been generalized for any number of CPUs, mostly because the i.MX6 has a both dual and quad core variants. However it might be better to include the generalized logic in the main armpmu code. I think the logic could be deployed automatically on SMP systems with only a single not-percpu IRQ, replacing the plat->handle_irq dance we currently do to hook up this code. Thoughts? (or is there already shared logic to do this that I overlooked) arch/arm/mach-imx/mach-imx6q.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) -- 1.9.3 diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index d51c6e99a2e9..c056b7b97eaa 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ #include #include #include +#include #include #include "common.h" @@ -261,6 +263,40 @@ static void __init imx6q_axi_init(void) } } +/* + * The PMU IRQ lines of all cores are muxed onto a single interrupt. + * Rotate the interrupt around the cores if the current CPU cannot + * figure out why the interrupt has been triggered. + */ +static irqreturn_t imx6q_pmu_handler(int irq, void *dev, irq_handler_t handler) +{ + irqreturn_t ret = handler(irq, dev); + int next; + + if (ret == IRQ_NONE && num_online_cpus() > 1) { + next = cpumask_next(smp_processor_id(), cpu_online_mask); + if (next > nr_cpu_ids) + next = cpumask_next(-1, cpu_online_mask); + irq_set_affinity(irq, cpumask_of(next)); + } + + /* + * We should be able to get away with the amount of IRQ_NONEs we give, + * while still having the spurious IRQ detection code kick in if the + * interrupt really starts hitting spuriously. + */ + return ret; +} + +static struct arm_pmu_platdata imx6q_pmu_platdata = { + .handle_irq = imx6q_pmu_handler, +}; + +static struct of_dev_auxdata imx6q_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &imx6q_pmu_platdata), + {}, +}; + static void __init imx6q_init_machine(void) { struct device *parent; @@ -276,7 +312,8 @@ static void __init imx6q_init_machine(void) imx6q_enet_phy_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); + of_platform_populate(NULL, of_default_bus_match_table, + imx6q_auxdata_lookup, parent); imx_anatop_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();