From patchwork Fri Nov 21 16:24:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5356241 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F101EC11AC for ; Fri, 21 Nov 2014 16:27:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D69EC2017E for ; Fri, 21 Nov 2014 16:27:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F25120176 for ; Fri, 21 Nov 2014 16:27:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xrr1u-0005YW-Ui; Fri, 21 Nov 2014 16:25:54 +0000 Received: from mail-wi0-f179.google.com ([209.85.212.179]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xrr1B-0003if-DJ for linux-arm-kernel@lists.infradead.org; Fri, 21 Nov 2014 16:25:10 +0000 Received: by mail-wi0-f179.google.com with SMTP id ex7so9466020wid.6 for ; Fri, 21 Nov 2014 08:24:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HbJBoXeDUrRw30HVu6cN7Zn4INc5Oxevti2YrcOL5Jk=; b=mBH7gtQ14eqyGWggG+MZa8RhQG0B6A9aW6U9Ze3g+qnkVJXRh7aSCYwu0Bsgnr4E3P CrDV4CHVsaHgdKDEXYhSkAdSvoNOIrGMeNK5Tjtf93DvSGSz3F0ZAYJ5wOWdk9YZzMlV 4dS1AXhDaTDMHyUWasYe/Py+dOQwyiu6zmao4Wjk1HK3/bmtb2LpW0xVaDrMycgR0Usi jwMedPDnwf7JdjMnpX/dU6ghmn1XieeK3K0MzVVO4kjjERWa1m/CAFd+CCBHl52Ziyrp J0AgNzRbUsii7jJyJDuzA9MU2a9PZznDiuHkB7lIhMaBsb2Hu6Nvt4BBdHeYai+yXPI9 872w== X-Gm-Message-State: ALoCoQk8QJXVQ5hUgkojd5uPX2XEtphk8FLoTFKN+3wfK+cSYnlduCFc9C1BsxU9wiZOSQWgwtzY X-Received: by 10.194.3.2 with SMTP id 2mr9088131wjy.89.1416587084880; Fri, 21 Nov 2014 08:24:44 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id g16sm8661348wjq.20.2014.11.21.08.24.43 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Nov 2014 08:24:44 -0800 (PST) From: Daniel Thompson To: Russell King , Will Deacon , Catalin Marinas Subject: [PATCH v2 2/2] arm64: perf: Prevent wraparound during overflow Date: Fri, 21 Nov 2014 16:24:27 +0000 Message-Id: <1416587067-3220-3-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1416587067-3220-1-git-send-email-daniel.thompson@linaro.org> References: <1416412346-8759-1-git-send-email-daniel.thompson@linaro.org> <1416587067-3220-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141121_082509_648294_F372E124 X-CRM114-Status: GOOD ( 13.84 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Peter Zijlstra , patches@linaro.org, linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Ingo Molnar , Paul Mackerras , John Stultz , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the overflow threshold for a counter is set above or near the 0xffffffff boundary then the kernel may lose track of the overflow causing only events that occur *after* the overflow to be recorded. Specifically the problem occurs when the value of the performance counter overtakes its original programmed value due to wrap around. Typical solutions to this problem are either to avoid programming in values likely to be overtaken or to treat the overflow bit as the 33rd bit of the counter. Its somewhat fiddly to refactor the code to correctly handle the 33rd bit during irqsave sections (context switches for example) so instead we take the simpler approach of avoiding values likely to be overtaken. We set the limit to half of max_period because this matches the limit imposed in __hw_perf_event_init(). This causes a doubling of the interrupt rate for large threshold values, however even with a very fast counter ticking at 4GHz the interrupt rate would only be ~1Hz. Signed-off-by: Daniel Thompson --- arch/arm64/kernel/perf_event.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index aa29ecb4f800..25a5308744b1 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -169,8 +169,14 @@ armpmu_event_set_period(struct perf_event *event, ret = 1; } - if (left > (s64)armpmu->max_period) - left = armpmu->max_period; + /* + * Limit the maximum period to prevent the counter value + * from overtaking the one we are about to program. In + * effect we are reducing max_period to account for + * interrupt latency (and we are being very conservative). + */ + if (left > (armpmu->max_period >> 1)) + left = armpmu->max_period >> 1; local64_set(&hwc->prev_count, (u64)-left);