From patchwork Mon Nov 24 07:02:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonny Rao X-Patchwork-Id: 5363671 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9952D9F319 for ; Mon, 24 Nov 2014 07:05:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4C0020374 for ; Mon, 24 Nov 2014 07:05:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9860D20357 for ; Mon, 24 Nov 2014 07:05:37 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xsng5-0005jT-UC; Mon, 24 Nov 2014 07:03:17 +0000 Received: from mail-ig0-f201.google.com ([209.85.213.201]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xsng3-0005gJ-4r for linux-arm-kernel@lists.infradead.org; Mon, 24 Nov 2014 07:03:15 +0000 Received: by mail-ig0-f201.google.com with SMTP id h15so332336igd.2 for ; Sun, 23 Nov 2014 23:02:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=XjQyxEeI4OyhPXk2kH23qU1lqV64M+BVyCB48x6NMHk=; b=LVWgw1Yss+5EuoVnL/yp5PfNCODssuU4pXBcF8SvZF2Z2uv5Q0oNTA9CSqo4eT7Om5 tKbciXc4KXAXvBDHOVar6nDacnZZo1f+6MJxSPoLitQjG8S7M8x/CUWPZP3QJyEcmaw6 lld2BtnMJqiO5/K1UZRQYmV3B9nzIkeCgjGsp6652C9/JMftw6lsW3IqQioxh6+W7p7i u9lk31rpHDTOc8or84ZfLgl6VrNT/wnpMTvdzZJD6BDL5qS5ShVs/r9x049/WwLppZ5u KVQciyleX+S6sXuStB2gPBPILUelifsmxJomek5K13ntjMhh2Ib+bYyptuSarAkMCY9Y gvxQ== X-Gm-Message-State: ALoCoQkl+EEFEpAapaGBmu6rjTcLP81PRva/zAXbG4oFfftCKwTICv5oH4yHv/bme1OkUVKGGTO6 X-Received: by 10.182.81.74 with SMTP id y10mr18735949obx.22.1416812568662; Sun, 23 Nov 2014 23:02:48 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id t24si419978yht.2.2014.11.23.23.02.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 23 Nov 2014 23:02:48 -0800 (PST) Received: from sonnyrao.mtv.corp.google.com ([172.22.65.176]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id STwMcsX0.1; Sun, 23 Nov 2014 23:02:48 -0800 Received: by sonnyrao.mtv.corp.google.com (Postfix, from userid 129445) id D4569A08E8; Sun, 23 Nov 2014 23:02:46 -0800 (PST) From: Sonny Rao To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5] clocksource: arch_timer: Fix code to use physical timers when requested Date: Sun, 23 Nov 2014 23:02:44 -0800 Message-Id: <1416812564-26465-1-git-send-email-sonnyrao@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141123_230315_269997_89EF3885 X-CRM114-Status: GOOD ( 16.74 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , Lorenzo Pieralisi , Russell King , Sudeep KarkadaNagesha , Catalin Marinas , Daniel Lezcano , Will Deacon , linux-kernel@vger.kernel.org, stable@vger.kernel.org, dianders@chromium.org, Marc Zyngier , Sudeep Holla , Olof Johansson , Thomas Gleixner , Sonny Rao , Stephen Boyd X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a bug fix for using physical arch timers when the arch_timer_use_virtual boolean is false. It restores the arch_counter_get_cntpct() function after removal in 0d651e4e "clocksource: arch_timer: use virtual counters" We need this on certain ARMv7 systems which are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) One example of such as system is RK3288 where it is much simpler to use the physical counter since there's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Fixes: 0d651e4e65e9 ("clocksource: arch_timer: use virtual counters") Cc: stable@vger.kernel.org Signed-off-by: Sonny Rao Acked-by: Olof Johansson Acked-by: Catalin Marinas Acked-by: Daniel Lezcano --- v2: Add fixes tag to commit message, cc stable, copy Doug's description of the systems which need this in commit message. v3: Don't change the memory-mapped physical timer/counter code v4: remove the memory-mapped physical counter code since it's not used v5: rebase and make AArch64 version of arch_counter_get_cntpct call BUG() --- arch/arm/include/asm/arch_timer.h | 9 +++++++++ arch/arm64/include/asm/arch_timer.h | 9 +++++++++ drivers/clocksource/arm_arch_timer.c | 5 ++++- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 92793ba..d4ebf56 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -78,6 +78,15 @@ static inline u32 arch_timer_get_cntfrq(void) return val; } +static inline u64 arch_counter_get_cntpct(void) +{ + u64 cval; + + isb(); + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); + return cval; +} + static inline u64 arch_counter_get_cntvct(void) { u64 cval; diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index f190971..b1fa4e6 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -104,6 +104,15 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl) asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl)); } +static inline u64 arch_counter_get_cntpct(void) +{ + /* + * AArch64 kernel and user space mandate the use of CNTVCT. + */ + BUG(); + return 0; +} + static inline u64 arch_counter_get_cntvct(void) { u64 cval; diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 43005d4..1fa2af9 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -462,7 +462,10 @@ static void __init arch_counter_register(unsigned type) /* Register the CP15 based counter if we have one */ if (type & ARCH_CP15_TIMER) { - arch_timer_read_counter = arch_counter_get_cntvct; + if (arch_timer_use_virtual) + arch_timer_read_counter = arch_counter_get_cntvct; + else + arch_timer_read_counter = arch_counter_get_cntpct; } else { arch_timer_read_counter = arch_counter_get_cntvct_mem;