From patchwork Tue Nov 25 17:26:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5381651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7789F9F39D for ; Tue, 25 Nov 2014 17:31:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B5BE3201C0 for ; Tue, 25 Nov 2014 17:31:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2B1220142 for ; Tue, 25 Nov 2014 17:30:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XtJun-0003Ug-Lh; Tue, 25 Nov 2014 17:28:37 +0000 Received: from mail-wi0-f181.google.com ([209.85.212.181]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XtJuC-00032I-Sl for linux-arm-kernel@lists.infradead.org; Tue, 25 Nov 2014 17:28:02 +0000 Received: by mail-wi0-f181.google.com with SMTP id r20so2249335wiv.8 for ; Tue, 25 Nov 2014 09:27:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i95OY5U/IKXI0lxVDezdlMqr5dBpwhXCuWzKlmLo540=; b=efWS3cfCHsPdd4MJkRdnilXnjno4GfBNSPSLxm0q0frwOIMoKskZde3LS1wB/Aaai6 CXNM80wvflw+KaEL+VqXO3yff0dJZsmuQqatrbVzw52vaTQkrtMTA00oE1IhGttvIODk 79PnS1T+Ems0tBlvLYVHQQnHLiBA5mh1iKKcaJW/AwM7otN8JXcqV6u6GzqeG0pMDwGZ aquQG9f0TX1NHe3BXG76lYCHrU7XlqkeTiV8Y2S3mlTKD8LG2FM9VBxDwB3tDZjCqzaC hqzLzOYYcq6+kK0bk8q24lErO77ZvxzElN7XL/6Iqtl4MYpmYQiflFaXXiLuhezuYrKr ldiw== X-Gm-Message-State: ALoCoQlYZrgm15wXHPKZKGXl/Wlbzqb83x7VKy4w4hebFYVkYTU46/I7sryuG6CQycigAQmubUKg X-Received: by 10.180.90.144 with SMTP id bw16mr34344156wib.50.1416936458704; Tue, 25 Nov 2014 09:27:38 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id c5sm3696725wik.3.2014.11.25.09.27.37 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Nov 2014 09:27:37 -0800 (PST) From: Daniel Thompson To: Thomas Gleixner , Jason Cooper Subject: [PATCH 3.18-rc3 v9 2/5] irqchip: gic: Make gic_raise_softirq() FIQ-safe Date: Tue, 25 Nov 2014 17:26:38 +0000 Message-Id: <1416936401-5147-3-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1416936401-5147-1-git-send-email-daniel.thompson@linaro.org> References: <1415968543-29469-1-git-send-email-daniel.thompson@linaro.org> <1416936401-5147-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141125_092801_113482_8035F8C4 X-CRM114-Status: GOOD ( 16.57 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , patches@linaro.org, Marc Zyngier , linux-kernel@vger.kernel.org, Daniel Drake , Dmitry Pervushin , Dirk Behme , John Stultz , Tim Sander , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It is currently possible for FIQ handlers to re-enter gic_raise_softirq() and lock up. gic_raise_softirq() lock(x); ---> FIQ handle_fiq() gic_raise_softirq() lock(x); <-- Lockup Calling printk() from a FIQ handler can trigger this problem because printk() raises an IPI when it needs to wake_up_klogd(). More generally, IPIs are the only means for FIQ handlers to safely defer work to less restrictive calling context so the function to raise them really needs to be FIQ-safe. This patch fixes the problem by converting the cpu_map_migration_lock into a rwlock making it safe to re-enter the function. Having made it safe to re-enter gic_raise_softirq() we no longer need to mask interrupts during gic_raise_softirq() because the b.L migration is always performed from task context. Signed-off-by: Daniel Thompson Cc: Thomas Gleixner Cc: Jason Cooper Cc: Russell King Cc: Marc Zyngier --- drivers/irqchip/irq-gic.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index bb4bc20573ea..a53aa11e4f17 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -75,8 +75,11 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock); /* * This lock is used by the big.LITTLE migration code to ensure no * IPIs can be pended on the old core after the map has been updated. + * + * This lock may be locked for reading from FIQ handlers and therefore + * must not be locked for writing when FIQs are enabled. */ -static DEFINE_RAW_SPINLOCK(cpu_map_migration_lock); +static DEFINE_RWLOCK(cpu_map_migration_lock); /* * The GIC mapping of CPU interfaces does not necessarily match @@ -625,12 +628,20 @@ static void __init gic_pm_init(struct gic_chip_data *gic) #endif #ifdef CONFIG_SMP +/* + * Raise the specified IPI on all cpus set in mask. + * + * This function is safe to call from all calling contexts, including + * FIQ handlers. It relies on read locks being multiply acquirable to + * avoid deadlocks when the function is re-entered at different + * exception levels. + */ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) { int cpu; - unsigned long flags, map = 0; + unsigned long map = 0; - raw_spin_lock_irqsave(&cpu_map_migration_lock, flags); + read_lock(&cpu_map_migration_lock); /* Convert our logical CPU mask into a physical one. */ for_each_cpu(cpu, mask) @@ -645,7 +656,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) /* this always happens on GIC0 */ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); - raw_spin_unlock_irqrestore(&cpu_map_migration_lock, flags); + read_unlock(&cpu_map_migration_lock); } #endif @@ -693,7 +704,8 @@ int gic_get_cpu_id(unsigned int cpu) * Migrate all peripheral interrupts with a target matching the current CPU * to the interface corresponding to @new_cpu_id. The CPU interface mapping * is also updated. Targets to other CPU interfaces are unchanged. - * This must be called with IRQs locally disabled. + * This must be called from a task context and with IRQ and FIQ locally + * disabled. */ void gic_migrate_target(unsigned int new_cpu_id) { @@ -724,9 +736,9 @@ void gic_migrate_target(unsigned int new_cpu_id) * pending on the old cpu static. That means we can defer the * migration until after we have released the irq_controller_lock. */ - raw_spin_lock(&cpu_map_migration_lock); + write_lock(&cpu_map_migration_lock); gic_cpu_map[cpu] = 1 << new_cpu_id; - raw_spin_unlock(&cpu_map_migration_lock); + write_unlock(&cpu_map_migration_lock); /* * Find all the peripheral interrupts targetting the current