From patchwork Wed Dec 10 10:50:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?RWRkaWUgSHVhbmcgKOm7g+aZuuWCkSk=?= X-Patchwork-Id: 5467941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C715EBEEA8 for ; Wed, 10 Dec 2014 10:55:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C5A3A20121 for ; Wed, 10 Dec 2014 10:55:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C66FB20125 for ; Wed, 10 Dec 2014 10:54:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xyesx-0006VL-Sd; Wed, 10 Dec 2014 10:52:47 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XyesD-0005vg-9E for linux-arm-kernel@lists.infradead.org; Wed, 10 Dec 2014 10:52:02 +0000 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 60175800; Wed, 10 Dec 2014 18:51:39 +0800 Received: from mtkslt208.mediatek.inc (10.21.15.95) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Wed, 10 Dec 2014 18:51:37 +0800 From: Eddie Huang To: Matthias Brugger , Rob Herring , Jason Cooper Subject: [PATCH 3/4] arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile Date: Wed, 10 Dec 2014 18:50:01 +0800 Message-ID: <1418208602-35584-4-git-send-email-eddie.huang@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1418208602-35584-1-git-send-email-eddie.huang@mediatek.com> References: <1418208602-35584-1-git-send-email-eddie.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141210_025201_777514_45339F18 X-CRM114-Status: GOOD ( 11.11 ) X-Spam-Score: 1.3 (+) Cc: Mark Rutland , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Pawel Moll , Ian Campbell , Catalin Marinas , Mark Brown , Will Deacon , linux-kernel@vger.kernel.org, Robert Richter , Sascha Hauer , Kumar Gala , Olof Johansson , "Joe.C" , Thomas Gleixner , Eddie Huang , linux-arm-kernel@lists.infradead.org, yh.chen@mediatek.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree support for MT8173 SoC and evalutaion board based on it. Signed-off-by: Eddie Huang --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/mt8173-evb.dts | 31 +++++++ arch/arm64/boot/dts/mt8173.dtsi | 164 +++++++++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/mt8173-evb.dts create mode 100644 arch/arm64/boot/dts/mt8173.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f8001a6..db7661e 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb diff --git a/arch/arm64/boot/dts/mt8173-evb.dts b/arch/arm64/boot/dts/mt8173-evb.dts new file mode 100644 index 0000000..adf26dd --- /dev/null +++ b/arch/arm64/boot/dts/mt8173-evb.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Eddie Huang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt8173.dtsi" + +/ { + model = "mediatek,mt8173-evb"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mt8173.dtsi b/arch/arm64/boot/dts/mt8173.dtsi new file mode 100644 index 0000000..1286801 --- /dev/null +++ b/arch/arm64/boot/dts/mt8173.dtsi @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Eddie Huang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt8173"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x101>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + clk26m: clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk32k: clk32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <1 13 0x8>, + <1 14 0x8>, + <1 11 0x8>, + <1 10 0x8>; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10220000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x1000>, + <0 0x10200620 0 0x1000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8173-uart","mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <0 83 8>; + clocks = <&uart_clk>; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8173-uart","mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <0 84 8>; + clocks = <&uart_clk>; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8173-uart","mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <0 85 8>; + clocks = <&uart_clk>; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt8173-uart","mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <0 86 8>; + clocks = <&uart_clk>; + }; + }; + +}; +