From patchwork Thu Dec 11 14:23:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 5476211 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 184A49F2E8 for ; Thu, 11 Dec 2014 14:29:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 09EBD20166 for ; Thu, 11 Dec 2014 14:29:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D521F20172 for ; Thu, 11 Dec 2014 14:29:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xz4hX-0001Rm-5T; Thu, 11 Dec 2014 14:26:43 +0000 Received: from service88.mimecast.com ([195.130.217.12]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xz4hQ-0001K0-4L for linux-arm-kernel@lists.infradead.org; Thu, 11 Dec 2014 14:26:37 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Thu, 11 Dec 2014 14:24:03 +0000 Received: from e106794-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 11 Dec 2014 14:24:02 +0000 From: Jean-Philippe Brucker To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/4] arm64: GICv3: change unsigned types for AArch32 compatibility Date: Thu, 11 Dec 2014 14:23:06 +0000 Message-Id: <1418307788-17977-3-git-send-email-jean-philippe.brucker@arm.com> X-Mailer: git-send-email 2.2.0.rc1 In-Reply-To: <1418307788-17977-1-git-send-email-jean-philippe.brucker@arm.com> References: <1418307788-17977-1-git-send-email-jean-philippe.brucker@arm.com> X-OriginalArrivalTime: 11 Dec 2014 14:24:02.0529 (UTC) FILETIME=[1C9AE510:01D0154E] X-MC-Unique: 114121114240309201 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141211_062636_506355_5CF394DA X-CRM114-Status: GOOD ( 11.95 ) X-Spam-Score: -2.3 (--) Cc: marc.zyngier@arm.com, Jean-Philippe Brucker X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch does a few simple compatibility-related changes: - change the system register access prototypes to their actual size, - homogenise mpidr accesses with unsigned long, - force the 64bit register values to unsigned long long. Note: the list registers are 64bit on GICv3, but the AArch32 vGIC driver will need to split their values into two 32bit registers: LRn and LRCn. Signed-off-by: Jean-Philippe Brucker --- arch/arm64/include/asm/arch_gicv3.h | 31 ++++++++++++++++++------------- drivers/irqchip/irq-gic-v3.c | 25 ++++++++++++------------- include/linux/irqchip/arm-gic-v3.h | 18 +++++++++--------- 3 files changed, 39 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index 28482d0..a0ea9de 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -77,15 +77,20 @@ #include -/* Low level accessors */ +/* + * Low-level accessors + * + * These system registers are 32 bits, but we make sure that the compiler + * sets the GP register's most significant bits to 0 with an explicit cast. + */ -static inline void gic_write_eoir(u64 irq) +static inline void gic_write_eoir(u32 irq) { - asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); + asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq)); isb(); } -static inline u64 __maybe_unused gic_read_iar(void) +static inline u32 __maybe_unused gic_read_iar(void) { u64 irqstat; @@ -93,20 +98,20 @@ static inline u64 __maybe_unused gic_read_iar(void) return irqstat; } -static inline void __maybe_unused gic_write_pmr(u64 val) +static inline void __maybe_unused gic_write_pmr(u32 val) { - asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); + asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val)); } -static inline void __maybe_unused gic_write_ctlr(u64 val) +static inline void __maybe_unused gic_write_ctlr(u32 val) { - asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); + asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val)); isb(); } -static inline void __maybe_unused gic_write_grpen1(u64 val) +static inline void __maybe_unused gic_write_grpen1(u32 val) { - asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); + asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val)); isb(); } @@ -115,7 +120,7 @@ static inline void __maybe_unused gic_write_sgi1r(u64 val) asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); } -static inline u64 __maybe_unused gic_read_sre(void) +static inline u32 __maybe_unused gic_read_sre(void) { u64 val; @@ -123,9 +128,9 @@ static inline u64 __maybe_unused gic_read_sre(void) return val; } -static inline void __maybe_unused gic_write_sre(u64 val) +static inline void __maybe_unused gic_write_sre(u32 val) { - asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); + asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val)); isb(); } diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index b85d6b6..e2cd5ac 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -220,11 +220,11 @@ static int gic_set_type(struct irq_data *d, unsigned int type) return 0; } -static u64 gic_mpidr_to_affinity(u64 mpidr) +static u64 gic_mpidr_to_affinity(unsigned long mpidr) { u64 aff; - aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | + aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); @@ -234,7 +234,7 @@ static u64 gic_mpidr_to_affinity(u64 mpidr) static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) { - u64 irqnr; + u32 irqnr; do { irqnr = gic_read_iar(); @@ -285,9 +285,9 @@ static void __init gic_dist_init(void) writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); } -static int gic_populate_rdist(void) +static int __init gic_populate_rdist(void) { - u64 mpidr = cpu_logical_map(smp_processor_id()); + unsigned long mpidr = cpu_logical_map(smp_processor_id()); u64 typer; u32 aff; int i; @@ -316,9 +316,8 @@ static int gic_populate_rdist(void) typer = readq_relaxed(ptr + GICR_TYPER); if ((typer >> 32) == aff) { gic_data_rdist_rd_base() = ptr; - pr_info("CPU%d: found redistributor %llx @%p\n", - smp_processor_id(), - (unsigned long long)mpidr, ptr); + pr_info("CPU%d: found redistributor %lx @%p\n", + smp_processor_id(), mpidr, ptr); return 0; } @@ -333,8 +332,8 @@ static int gic_populate_rdist(void) } /* We couldn't even deal with ourselves... */ - WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", - smp_processor_id(), (unsigned long long)mpidr); + WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", + smp_processor_id(), mpidr); return -ENODEV; } @@ -403,10 +402,10 @@ static struct notifier_block gic_cpu_notifier = { }; static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, - u64 cluster_id) + unsigned long cluster_id) { int cpu = *base_cpu; - u64 mpidr = cpu_logical_map(cpu); + unsigned long mpidr = cpu_logical_map(cpu); u16 tlist = 0; while (cpu < nr_cpu_ids) { @@ -463,7 +462,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) smp_wmb(); for_each_cpu_mask(cpu, *mask) { - u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; + unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; u16 tlist; tlist = gic_compute_target_list(&cpu, mask, cluster_id); diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index e70b56f..95171d1 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -39,7 +39,7 @@ #define GICD_ICACTIVER 0x0380 #define GICD_IPRIORITYR 0x0400 #define GICD_ICFGR 0x0C00 -#define GICD_IROUTER 0x6000 +#define GICD_IROUTER 0x6000 /* 64bit */ #define GICD_PIDR2 0xFFE8 #define GICD_CTLR_RWP (1U << 31) @@ -61,7 +61,7 @@ #define GICR_IIDR 0x0004 #define GICR_TYPER 0x0008 #define GICR_STATUSR GICD_STATUSR -#define GICR_WAKER 0x0014 +#define GICR_WAKER 0x0014 /* 32bit */ #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 #define GICR_SEIR GICD_SEIR @@ -69,7 +69,7 @@ #define GICR_PENDBASER 0x0078 #define GICR_INVLPIR 0x00A0 #define GICR_INVALLR 0x00B0 -#define GICR_SYNCR 0x00C0 +#define GICR_SYNCR 0x00C0 /* 32bit */ #define GICR_MOVLPIR 0x0100 #define GICR_MOVALLR 0x0110 #define GICR_PIDR2 GICD_PIDR2 @@ -107,13 +107,13 @@ /* * Hypervisor interface registers (SRE only) */ -#define ICH_LR_VIRTUAL_ID_MASK ((1UL << 32) - 1) +#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) -#define ICH_LR_EOI (1UL << 41) -#define ICH_LR_GROUP (1UL << 60) -#define ICH_LR_STATE (3UL << 62) -#define ICH_LR_PENDING_BIT (1UL << 62) -#define ICH_LR_ACTIVE_BIT (1UL << 63) +#define ICH_LR_EOI (1ULL << 41) +#define ICH_LR_GROUP (1ULL << 60) +#define ICH_LR_STATE (3ULL << 62) +#define ICH_LR_PENDING_BIT (1ULL << 62) +#define ICH_LR_ACTIVE_BIT (1ULL << 63) #define ICH_MISR_EOI (1 << 0) #define ICH_MISR_U (1 << 1)