From patchwork Thu Dec 11 14:23:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 5476201 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 258C29F2E8 for ; Thu, 11 Dec 2014 14:29:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 39F7520166 for ; Thu, 11 Dec 2014 14:29:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DB4320149 for ; Thu, 11 Dec 2014 14:29:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xz4hz-0001cN-3I; Thu, 11 Dec 2014 14:27:11 +0000 Received: from service88.mimecast.com ([195.130.217.12]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xz4hR-0001Jw-VU for linux-arm-kernel@lists.infradead.org; Thu, 11 Dec 2014 14:26:39 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Thu, 11 Dec 2014 14:24:03 +0000 Received: from e106794-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 11 Dec 2014 14:24:02 +0000 From: Jean-Philippe Brucker To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] arm64: GICv3: Specialize readq and writeq accesses Date: Thu, 11 Dec 2014 14:23:07 +0000 Message-Id: <1418307788-17977-4-git-send-email-jean-philippe.brucker@arm.com> X-Mailer: git-send-email 2.2.0.rc1 In-Reply-To: <1418307788-17977-1-git-send-email-jean-philippe.brucker@arm.com> References: <1418307788-17977-1-git-send-email-jean-philippe.brucker@arm.com> X-OriginalArrivalTime: 11 Dec 2014 14:24:02.0795 (UTC) FILETIME=[1CC37BB0:01D0154E] X-MC-Unique: 114121114240313501 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141211_062638_400282_B0A99796 X-CRM114-Status: GOOD ( 10.65 ) X-Spam-Score: -2.3 (--) Cc: marc.zyngier@arm.com, Jean-Philippe Brucker X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 32bit platforms, we cannot assure that an I/O ldrd or strd will be done atomically. Besides, an hypervisor would be unable to emulate such accesses. In order to allow the AArch32 version of the driver to split them into two 32bit accesses while keeping the requirement for atomic writes, this patch specializes the IROUTER and TYPER accesses. Since the latter is an ID register, it won't need to be read atomically, but we still avoid future confusion by using gic_read_typer instead of a generic gic_readq. Signed-off-by: Jean-Philippe Brucker --- arch/arm64/include/asm/arch_gicv3.h | 3 +++ drivers/irqchip/irq-gic-v3.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index a0ea9de..622f08a 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -134,5 +134,8 @@ static inline void __maybe_unused gic_write_sre(u32 val) isb(); } +#define gic_read_typer(c) readq_relaxed(c) +#define gic_write_irouter(v, c) writeq_relaxed(v, c) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_GICV3_H */ diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index e2cd5ac..d8f30ee 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -282,7 +282,7 @@ static void __init gic_dist_init(void) */ affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); for (i = 32; i < gic_data.irq_nr; i++) - writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); + gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); } static int __init gic_populate_rdist(void) @@ -313,7 +313,7 @@ static int __init gic_populate_rdist(void) } do { - typer = readq_relaxed(ptr + GICR_TYPER); + typer = gic_read_typer(ptr + GICR_TYPER); if ((typer >> 32) == aff) { gic_data_rdist_rd_base() = ptr; pr_info("CPU%d: found redistributor %lx @%p\n", @@ -498,7 +498,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); - writeq_relaxed(val, reg); + gic_write_irouter(val, reg); /* * If the interrupt was enabled, enabled it again. Otherwise,