From patchwork Thu Dec 11 20:21:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 5477491 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 707EA9F1CD for ; Thu, 11 Dec 2014 20:25:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 66535201BB for ; Thu, 11 Dec 2014 20:25:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 64A43201B4 for ; Thu, 11 Dec 2014 20:25:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XzAGZ-0003uh-Jq; Thu, 11 Dec 2014 20:23:15 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XzAGA-0003eL-Ks for linux-arm-kernel@lists.infradead.org; Thu, 11 Dec 2014 20:22:52 +0000 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1XzAFb-0006uv-8T; Thu, 11 Dec 2014 21:22:15 +0100 Received: from str by dude.hi.pengutronix.de with local (Exim 4.84) (envelope-from ) id 1XzAFZ-0007hT-40; Thu, 11 Dec 2014 21:22:13 +0100 From: Steffen Trumtrar To: devicetree@vger.kernel.org Subject: [RFC 1/3] devicetree: bindings: Add SoCFpga HPS bridges Date: Thu, 11 Dec 2014 21:21:40 +0100 Message-Id: <1418329302-20813-2-git-send-email-s.trumtrar@pengutronix.de> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1418329302-20813-1-git-send-email-s.trumtrar@pengutronix.de> References: <1418329302-20813-1-git-send-email-s.trumtrar@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: str@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141211_122250_917574_17083AAA X-CRM114-Status: GOOD ( 13.89 ) X-Spam-Score: -0.0 (/) Cc: Mark Rutland , Pawel Moll , Ian Campbell , atull@opensource.altera.com, Rob Herring , kernel@pengutronix.de, Kumar Gala , Dinh Nguyen , Steffen Trumtrar , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From the datasheet: The HPS-FPGA bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic and vice versa. For example, you can instantiate additional memories or peripherals in the FPGA fabric, and master interfaces belonging to components in the HPS logic can access them. You can also instantiate components such as a NiosII processor in the FPGA fabric and their master interfaces can access memories or peripherals in the HPS logic This patch adds bindings for the three bridges on SoCFPGA: - hps2fpga (buswidths: 32, 64, 128 bits) - fpga2hps (buswidths: 32, 64, 128 bits) - lwhps2fpga (buswidth: 32 bits) Two of the bridges have a configurable buswidth (via bitstream). The bridges depend on the L3 NIC to be able to set bus visibility. Signed-off-by: Steffen Trumtrar --- .../soc/socfpga/altr,fpga2hps-axi-bridge.txt | 32 +++++++++++++ .../soc/socfpga/altr,hps2fpga-axi-bridge.txt | 54 ++++++++++++++++++++++ .../soc/socfpga/altr,lwhps2fpga-axi-bridge.txt | 31 +++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,fpga2hps-axi-bridge.txt create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,hps2fpga-axi-bridge.txt create mode 100644 Documentation/devicetree/bindings/soc/socfpga/altr,lwhps2fpga-axi-bridge.txt diff --git a/Documentation/devicetree/bindings/soc/socfpga/altr,fpga2hps-axi-bridge.txt b/Documentation/devicetree/bindings/soc/socfpga/altr,fpga2hps-axi-bridge.txt new file mode 100644 index 000000000000..0df0cfbe350d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socfpga/altr,fpga2hps-axi-bridge.txt @@ -0,0 +1,32 @@ +Altera SoCFPGA FPGA2HPS AXI Bridge +---------------------------------- + +Required properties: + - compatible : "altr,fpga2hps-axi-bridge" + - reg : Must contain one range: + - the register space for the bridge module configuration + - resets : The reset line for the module + - reset-names : Must include "fpga2hps" + - bus-width : the configured bus width of the bridge + - allowed values : 32, 64, 128 + +Optional properties: + - altr,bridge-gpv : a pointer to the GPV master for configuration purposes + - fpgamgr : A pointer to the FPGA-Manager. This is needed, if the FPGA + needs to be loaded before the bridges can be enabled. + +Example: + + fpga2hps: axibridge@ff600000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,fpga2hps-axi-bridge", "simple-bus"; + reg = <0xff600000 0x100000>; + clocks = <&l4_mp_clk>, <&l3_main_clk>; + clock-names = "gpv_clk", "data_clk"; + resets = <&rst FPGA2HPS_RESET>; + reset-names = "fpga2hps"; + altr,bridge-gpv = <&lwhps2fpga>; + bus-width = <64>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/soc/socfpga/altr,hps2fpga-axi-bridge.txt b/Documentation/devicetree/bindings/soc/socfpga/altr,hps2fpga-axi-bridge.txt new file mode 100644 index 000000000000..e5230639e5e4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socfpga/altr,hps2fpga-axi-bridge.txt @@ -0,0 +1,54 @@ +Altera SoCFPGA HPS2FPGA AXI Bridge +---------------------------------- + +Required properties: + - compatible : "altr,hps2fpga-axi-bridge" + - reg : Must contain two ranges: + 1. the register space for the bridge module configuration + 2. the address space for the bridge domain + - reg-names : Must include the entries: + "data" : Address space + "gpv" : Global Programmers View registers + - resets : The reset line for the module + - reset-names : Must include "hps2fpga" + - altr,l3-gpv : a pointer to the L3 NIC used for configuration + - bus-width : the configured bus width of the bridge + - allowed values : 32, 64, 128 + +Optional properties: + - altr,bridge-gpv : a pointer to the bridge GPV master for configuration + - fpgamgr : A pointer to the FPGA-Manager. This is needed, if the FPGA + needs to be loaded before the bridges can be enabled. + +Example: + + hps2fpga: axibridge@ff500000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,hps2fpga-axi-bridge"; + reg = <0xff500000 0x100000>, + <0xc0000000 0x3c000000>; + clocks = <&l4_mp_clk>, <&l3_main_clk>; + clock-names = "gpv_clk", "data_clk"; + resets = <&rst HPS2FPGA_RESET>; + reset-names = "hps2fpga"; + altr,gpv-master = <&lwhps2fpga>; + altr,l3-gpv = <&l3regs>; + bus-width = <64>; + status = "disabled"; + ranges; + }; + +Board file example: + + &hps2fpga { + bus-width = <32>; + status = "okay"; + + axi-ip: axi-ip@c0000000 { + compatible = "axi-ip"; + reg = <0xc0000000 0x10000>; + clocks = <&h2f_usr2_clk>; + status = "okay"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/socfpga/altr,lwhps2fpga-axi-bridge.txt b/Documentation/devicetree/bindings/soc/socfpga/altr,lwhps2fpga-axi-bridge.txt new file mode 100644 index 000000000000..e5664792a6f2 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socfpga/altr,lwhps2fpga-axi-bridge.txt @@ -0,0 +1,31 @@ +Altera SoCFPGA LWHPS2FPGA AXI Bridge +------------------------------------ + +Required properties: + - compatible : "altr,lwhps2fpga-axi-bridge" + - reg : Must contain two ranges: + 1. the register space for the bridge module configuration + 2. the address space for the bridge domain + - resets : The reset line for the module + - reset-names : Must include "lwhps2fpga" + - altr,l3-gpv : A pointer to the L3 NIC used for configuration +Optional properties: + - fpgamgr : A pointer to the FPGA-Manager. This is needed, if the + FPGA needs to be loaded before the bridges can be + enabled. + +Example: + + lwhps2fpga: axibridge@ff400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,lwhps2fpga-axi-bridge", "simple-bus"; + reg = <0xff400000 0x100000>, + <0xff200000 0x200000>; + clocks = <&l4_mp_clk>; + resets = <&rst LWHPS2FPGA_RESET>; + reset-names = "lwhps2fpga"; + altr,l3-gpv = <&l3regs>; + status = "disabled"; + ranges; + };