From patchwork Fri Dec 12 11:11:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 5481811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8C7119F1CD for ; Fri, 12 Dec 2014 11:14:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BE0322014A for ; Fri, 12 Dec 2014 11:14:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E62692013A for ; Fri, 12 Dec 2014 11:14:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XzO9I-0005Rk-OF; Fri, 12 Dec 2014 11:12:40 +0000 Received: from mail-wi0-f172.google.com ([209.85.212.172]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XzO9F-0005OW-3X for linux-arm-kernel@lists.infradead.org; Fri, 12 Dec 2014 11:12:37 +0000 Received: by mail-wi0-f172.google.com with SMTP id n3so2131829wiv.11 for ; Fri, 12 Dec 2014 03:12:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lwpwhT3LDarbFmK0utl9dHESMuZVmMxgzGUlQcRHVg0=; b=kZDS14o0fcfHtRY+yyMwsZ82aSJGi3KqW7ZdcHZSTAqo4IkUz136Io3RgoxO3Hol9T wkDYUiyCCAE0DvmQiPHb26LKEHxSmpxl8e/OJbMtsnU1agAZrEOk8OR5hXIdxnt/H+kB 3WG+CQ+o6gXJn6tB2S+V9hIWW1ARVH1yTSnvd55LH0c10J5pp0LgPgeIfnRdrdtStl00 6/T9sMRaZFf1zaBcBvOOZtR6RYkY4BOGG3nzo5NDgpvJRynEzSyMzMKpBaAhru8J2HTB tAu6IB5qXdr7GbdCVwoMUDCYtsLKyqCQd5VTGP4+rWXcJPojWMVbesuZKeB3P3qWKXJx QZEQ== X-Gm-Message-State: ALoCoQnKZHJGNPNRc4tC9YZ+vthBqzcECmKG5CGurGnPWkaG6ILMUaaxxtbFbgLqDKuaoSRi+bBZ X-Received: by 10.194.23.10 with SMTP id i10mr25566972wjf.11.1418382734773; Fri, 12 Dec 2014 03:12:14 -0800 (PST) Received: from sundance.lan (cpc4-aztw19-0-0-cust157.18-1.cable.virginm.net. [82.33.25.158]) by mx.google.com with ESMTPSA id d5sm1379973wjb.34.2014.12.12.03.12.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Dec 2014 03:12:13 -0800 (PST) From: Daniel Thompson To: Russell King Subject: [RFC PATCH] arm: Remove early stack deallocation from restore_user_regs Date: Fri, 12 Dec 2014 11:11:58 +0000 Message-Id: <1418382718-16323-1-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141212_031237_317214_64303A89 X-CRM114-Status: GOOD ( 13.49 ) X-Spam-Score: -0.7 (/) Cc: Daniel Thompson , linaro-kernel@lists.linaro.org, patches@linaro.org, linux-kernel@vger.kernel.org, John Stultz , Sumit Semwal , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently restore_user_regs deallocates the SVC stack early in its execution and relies on no exception being taken between the deallocation and the registers being restored. The introduction of a default FIQ handler that also uses the SVC stack breaks this assumption and can result in corrupted register state. This patch works around the problem by removing the early stack deallocation and using r2 as a temporary instead. I have not found a way to do this without introducing an extra mov instruction to the macro. Signed-off-by: Daniel Thompson --- Notes: I have recently started to hook up the PMU via FIQ (although its slightly hacky at present) and was seeing random userspace SEGVs when perf was running (after ~100,000 or so FIQs). Instrumenting the code eventually revealed that in almost all cases the last FIQ handler to run prior the SEGV had interrupted ret_to_user_from_irq or ret_fast_syscall. Very occasionally it was in the fault handling code (because that code runs as part of SEGV handling and the PMU is instrumenting that too). No SEGV problems have been observed since fixing the issue. This version of the patch has seen >7M FIQs and an older version (based on cpsid f) ran overnight. arch/arm/kernel/entry-header.S | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) -- 1.9.3 diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 4176df721bf0..1a0045abead7 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -253,21 +253,22 @@ .endm .macro restore_user_regs, fast = 0, offset = 0 - ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr - ldr lr, [sp, #\offset + S_PC]! @ get pc + mov r2, sp + ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr + ldr lr, [r2, #\offset + S_PC]! @ get pc msr spsr_cxsf, r1 @ save in spsr_svc #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K) @ We must avoid clrex due to Cortex-A15 erratum #830321 - strex r1, r2, [sp] @ clear the exclusive monitor + strex r1, r2, [r2] @ clear the exclusive monitor #endif .if \fast - ldmdb sp, {r1 - lr}^ @ get calling r1 - lr + ldmdb r2, {r1 - lr}^ @ get calling r1 - lr .else - ldmdb sp, {r0 - lr}^ @ get calling r0 - lr + ldmdb r2, {r0 - lr}^ @ get calling r0 - lr .endif mov r0, r0 @ ARMv5T and earlier require a nop @ after ldm {}^ - add sp, sp, #S_FRAME_SIZE - S_PC + add sp, sp, #\offset + S_FRAME_SIZE movs pc, lr @ return & move spsr_svc into cpsr .endm