From patchwork Fri Dec 12 17:13:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 5484431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9B0FE9F39D for ; Fri, 12 Dec 2014 17:20:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7D7D4201D3 for ; Fri, 12 Dec 2014 17:20:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8236A2010B for ; Fri, 12 Dec 2014 17:20:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XzTrM-0008Jw-M0; Fri, 12 Dec 2014 17:18:32 +0000 Received: from ns.mm-sol.com ([37.157.136.199] helo=extserv.mm-sol.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XzTr6-0007yq-1E for linux-arm-kernel@lists.infradead.org; Fri, 12 Dec 2014 17:18:17 +0000 Received: from localhost.localdomain (unknown [37.157.136.206]) by extserv.mm-sol.com (Postfix) with ESMTPSA id 733B5C844; Fri, 12 Dec 2014 19:17:53 +0200 (EET) From: Stanimir Varbanov To: Rob Herring , Kumar Gala , Mark Rutland , Grant Likely , Bjorn Helgaas , Kishon Vijay Abraham I , Russell King , Arnd Bergmann Subject: [PATCH 3/5] DT: PCI: qcom: Document PCIe devicetree bindings Date: Fri, 12 Dec 2014 19:13:59 +0200 Message-Id: <1418404441-5518-4-git-send-email-svarbanov@mm-sol.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1418404441-5518-1-git-send-email-svarbanov@mm-sol.com> References: <1418404441-5518-1-git-send-email-svarbanov@mm-sol.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141212_091816_505837_B63DE19F X-CRM114-Status: GOOD ( 10.52 ) X-Spam-Score: -0.0 (/) Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Stanimir Varbanov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document Qualcomm PCIe driver devicetree bindings. Signed-off-by: Stanimir Varbanov --- .../devicetree/bindings/pci/qcom,pcie.txt | 159 ++++++++++++++++++++ 1 files changed, 159 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt new file mode 100644 index 0000000..2331144 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -0,0 +1,159 @@ +* Qualcomm PCI express root complex + +- compatible: + Usage: required + Value type: + Definition: Value shall include "qcom,pcie" + +- reg: + Usage: required + Value type: + Definition: Four register ranges as listed in the reg-names property + +- reg-names: + Usage: required + Value type: + Definition: Must include the following entries + - "parf" Qualcomm specific registers + - "dbi" Designware PCIe registers + - "elbi" External local bus interface registers + - "config" PCIe configuration space + +- device_type: + Usage: required + Value type: + Definition: Should be "pci". As specified in designware-pcie.txt + +- #address-cells: + Usage: required + Value type: + Definition: Should be set to 3. As specified in designware-pcie.txt + +- #size-cells: + Usage: required + Value type: + Definition: Should be set 2. As specified in designware-pcie.txt + +- ranges: + Usage: required + Value type: + Definition: As specified in designware-pcie.txt + +- interrupts: + Usage: required + Value type: + Definition: MSI interrupt + +- interrupt-names: + Usage: required + Value type: + Definition: Should contain "msi" + +- #interrupt-cells: + Usage: required + Value type: + Definition: Should be 1. As specified in designware-pcie.txt + +- interrupt-map-mask: + Usage: required + Value type: + Definition: As specified in designware-pcie.txt + +- interrupt-map: + Usage: required + Value type: + Definition: As specified in designware-pcie.txt + +- clocks: + Usage: required + Value type: + Definition: Four clocks as listed in clock-names property + +- clock-names: + Usage: required + Value type: + Definition: Must include the following entries + - "aux" auxiliary (AUX) clock + - "iface" configuration AHB clock + - "bus_master" master AXI clock + - "bus_slave" slave AXI clock + +- resets: + Usage: required + Value type: + Definition: List of phandle and reset specifier pairs as listed + in reset-names property + +- reset-names: + Usage: required + Value type: + Definition: Should contain the following entries + - "core" core reset + +- -supply: + Usage: required + Value type: + Definition: List of phandles to the supply regulators + - "vdd_pc" collapsing and restoring power to peripheral +- gpios: + Usage: optional + Value type: + Definition: List of phandle and gpio specifier. Should include + - "perst" PCIe endpoint reset signal line + - "pewake" PCIe endpoint wake signal line + +- pinctrl-0: + Usage: required + Value type: + Definition: List of phandles pointing at a pin(s) configuration + +- pinctrl-names + Usage: required + Value type: + Definition: List of names of pinctrl-0 state + +* Example + + pcie0@fc520000 { + compatible = "qcom,pcie"; + reg = <0xfc520000 0x2000>, + <0xff000000 0x1000>, + <0xff001000 0x1000>, + <0xff002000 0x2000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ + 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* Memory */ + interrupts = <0 243 0>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "aux", "iface", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + + vdd_pc-supply = <&gdsc_pcie0>; + + phys = <&pciephy0>; + phy-names = "pciephy"; + + gpios = <&tlmm 70 0>; /* perst */ + + pinctrl-0 = <&pcie0_pins_default>; + pinctrl-names = "default"; + };