From patchwork Fri Dec 19 15:04:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylvain Rochet X-Patchwork-Id: 5520421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9FFE1BEEA8 for ; Fri, 19 Dec 2014 15:07:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B11E12013D for ; Fri, 19 Dec 2014 15:07:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4C2720154 for ; Fri, 19 Dec 2014 15:07:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y1z7H-00064L-Bc; Fri, 19 Dec 2014 15:05:19 +0000 Received: from mx-guillaumet.finsecur.com ([91.217.234.131] helo=guillaumet.finsecur.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Y1z7E-0004uZ-HD for linux-arm-kernel@lists.infradead.org; Fri, 19 Dec 2014 15:05:17 +0000 Received: from [172.16.8.13] (helo=spice.lan) by guillaumet.finsecur.com with esmtps (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1Y1z6o-0002LO-Rg; Fri, 19 Dec 2014 16:04:51 +0100 Received: from gradator by spice.lan with local (Exim 4.84) (envelope-from ) id 1Y1z6o-0007vo-KE; Fri, 19 Dec 2014 16:04:50 +0100 From: Sylvain Rochet To: wenyou.yang@atmel.com, nicolas.ferre@atmel.com, ludovic.desroches@atmel.com, alexandre.belloni@free-electrons.com, maxime.ripard@free-electrons.com, linux-arm-kernel@lists.infradead.org Date: Fri, 19 Dec 2014 16:04:43 +0100 Message-Id: <1419001483-30298-1-git-send-email-sylvain.rochet@finsecur.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: References: X-SA-Exim-Connect-IP: 172.16.8.13 X-SA-Exim-Mail-From: sylvain.rochet@finsecur.com X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Subject: [PATCH] pm: at91: pm_slowclock: improve reliability of suspend/resume X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on guillaumet.finsecur.com) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141219_070516_750759_8FA13853 X-CRM114-Status: GOOD ( 13.52 ) X-Spam-Score: -0.0 (/) Cc: Sylvain Rochet X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Assume USB PLL and PLL B are already stopped before entering sleep mode, print a warning if this isn't the case. Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if something went wrong instead of continuing in unknown condition. There is not much we can do if a PLL lock never ends, we are running in SRAM and we will not be able to connect back the sdram or ddram in order to be able to fire up a message or just panic. As a bonus, not decounting the timeout register in slow clock mode reduce cumulated suspend time and resume time from ~17ms to ~15ms. --- arch/arm/mach-at91/pm.c | 12 +++++ arch/arm/mach-at91/pm_slowclock.S | 101 ++------------------------------------ 2 files changed, 16 insertions(+), 97 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index d213a00..3b0d804 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -168,6 +168,18 @@ static int at91_pm_verify_clocks(void) } } + /* Drivers should have previously suspended USB PLL */ + if (at91_pmc_read(AT91_CKGR_UCKR) & AT91_PMC_UPLLEN) { + pr_err("AT91: PM - Suspend-to-RAM with USB PLL running\n"); + return 0; + } + + /* Drivers should have previously suspended PLL B */ + if (at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) { + pr_err("AT91: PM - Suspend-to-RAM with PLL B running\n"); + return 0; + } + return 1; } #endif diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index 6194749..530b996 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -33,12 +33,6 @@ */ #undef SLOWDOWN_MASTER_CLOCK -#define MCKRDY_TIMEOUT 1000 -#define MOSCRDY_TIMEOUT 1000 -#define PLLALOCK_TIMEOUT 1000 -#define PLLBLOCK_TIMEOUT 1000 -#define UPLLLOCK_TIMEOUT 1000 - pmc .req r0 sdramc .req r1 ramc1 .req r2 @@ -46,76 +40,32 @@ memctrl .req r3 tmp1 .req r4 tmp2 .req r5 ddrcid .req r6 -flag .req r7 /* * Wait until master clock is ready (after switching master clock source) */ .macro wait_mckrdy - mov tmp2, #MCKRDY_TIMEOUT -1: sub tmp2, tmp2, #1 - cmp tmp2, #0 - beq 2f - ldr tmp1, [pmc, #AT91_PMC_SR] +1: ldr tmp1, [pmc, #AT91_PMC_SR] tst tmp1, #AT91_PMC_MCKRDY beq 1b -2: .endm /* * Wait until master oscillator has stabilized. */ .macro wait_moscrdy - mov tmp2, #MOSCRDY_TIMEOUT -1: sub tmp2, tmp2, #1 - cmp tmp2, #0 - beq 2f - ldr tmp1, [pmc, #AT91_PMC_SR] +1: ldr tmp1, [pmc, #AT91_PMC_SR] tst tmp1, #AT91_PMC_MOSCS beq 1b -2: .endm /* * Wait until PLLA has locked. */ .macro wait_pllalock - mov tmp2, #PLLALOCK_TIMEOUT -1: sub tmp2, tmp2, #1 - cmp tmp2, #0 - beq 2f - ldr tmp1, [pmc, #AT91_PMC_SR] +1: ldr tmp1, [pmc, #AT91_PMC_SR] tst tmp1, #AT91_PMC_LOCKA beq 1b -2: - .endm - -/* - * Wait until PLLB has locked. - */ - .macro wait_pllblock - mov tmp2, #PLLBLOCK_TIMEOUT -1: sub tmp2, tmp2, #1 - cmp tmp2, #0 - beq 2f - ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_LOCKB - beq 1b -2: - .endm - -/* - * Wait until UTMI PLL has locked. - */ - .macro wait_uplllock - mov tmp2, #UPLLLOCK_TIMEOUT -1: sub tmp2, tmp2, #1 - cmp tmp2, #0 - beq 2f - ldr tmp1, [pmc, #AT91_PMC_SR] - tst tmp1, #AT91_PMC_LOCKU - beq 1b -2: .endm /* @@ -126,6 +76,7 @@ flag .req r7 #if defined(CONFIG_CPU_V7) dsb + /* Disable the processor clock */ mov tmp1, #AT91_PMC_PCK str tmp1, [pmc, #AT91_PMC_SCDR] @@ -234,25 +185,6 @@ sdr_sr_done: mov tmp1, #AT91_PMC_SYS_DDR str tmp1, [pmc, #AT91_PMC_SCDR] - /* Save PLLB setting and disable it */ - ldr tmp1, [pmc, #AT91_CKGR_PLLBR] - str tmp1, .saved_pllbr - - mov tmp1, #AT91_PMC_PLLCOUNT - str tmp1, [pmc, #AT91_CKGR_PLLBR] - - /* Disable UTMI PLL */ - ldr tmp1, [pmc, #AT91_CKGR_UCKR] - tst tmp1, #AT91_PMC_UPLLEN - beq 1f - mov flag, #1 - bic tmp1, tmp1, #AT91_PMC_UPLLEN - str tmp1, [pmc, #AT91_CKGR_UCKR] - b 2f -1: - mov flag, #0 -2: - /* Save Master clock setting */ ldr tmp1, [pmc, #AT91_PMC_MCKR] str tmp1, .saved_mckr @@ -338,28 +270,6 @@ sdr_sr_done: wait_mckrdy - /* Turn on UTMI PLL */ - cmp flag, #1 - bne 1f - ldr tmp1, [pmc, #AT91_CKGR_UCKR] - orr tmp1, tmp1, #AT91_PMC_UPLLEN - str tmp1, [pmc, #AT91_CKGR_UCKR] - - wait_uplllock -1: - - /* Restore PLLB setting */ - ldr tmp1, .saved_pllbr - str tmp1, [pmc, #AT91_CKGR_PLLBR] - - tst tmp1, #(AT91_PMC_MUL & 0xff0000) - bne 1f - tst tmp1, #(AT91_PMC_MUL & ~0xff0000) - beq 2f -1: - wait_pllblock -2: - /* Enable MPDDRC Clock*/ cmp ddrcid, #0 beq 4f @@ -421,9 +331,6 @@ ram_restored: .saved_pllar: .word 0 -.saved_pllbr: - .word 0 - .saved_sam9_lpr: .word 0