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Mon, 22 Dec 2014 21:20:02 +0900 (KST) From: Alim Akhtar To: linux-mmc@vger.kernel.org Subject: [PATCH v3 3/3] mmc: dw_mmc: exynos: move definitions to header file Date: Mon, 22 Dec 2014 17:42:04 +0530 Message-id: <1419250324-11743-4-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.2.0 In-reply-to: <1419250324-11743-1-git-send-email-alim.akhtar@samsung.com> References: <1419250324-11743-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJLMWRmVeSWpSXmKPExsVy+t8zQ90inhkhBo13dS2W3qq2mHB5O6PF 2WUH2Sxu/Gpjtdj0+BqrxZH//YwWH+5fZLY4vjbcgcNjdsNFFo+ds+6ye9y5tofNY/OSeo8b rxYyefRtWcXo8XmTXAB7FJdNSmpOZllqkb5dAlfGx9NT2QomaVXMXr6euYHxjnIXIyeHhICJ xMnWNmYIW0ziwr31bF2MXBxCAssYJZo2PGSHKbqxaw8jRGI6o8SpOV2sEM4EJokby3rZQKrY BLQl7k7fwgRiiwjISvz8cwFsFLPAJkaJFZ9/soIkhAV8JFb0PgQrYhFQlVg8bT3Ybl4Bd4n+ NwdZINbJSWy59QhsNaeAh8TlOQ/A6oWAap7vuc4MMlRCYB27xKs559kgBglIfJt8CKiZAygh K7HpANQ/khIHV9xgmcAovICRYRWjaGpBckFxUnqRkV5xYm5xaV66XnJ+7iZGSAz07WC8ecD6 EKMAB6MSD29CxvQQIdbEsuLK3EOMpkAbJjJLiSbnAyMtryTe0NjMyMLUxNTYyNzSTEmcN0Hq Z7CQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxkk3Ou6pbAjZ8b757yuWtLRrYR/2Na+aHOXW wXX7UOilBW3L7XK6I/4s3/v05jOhRAXZ23qLGteXOy4//Jaf/cFxnaVWqT+FGw55T1wbtOsv z0P+itSdq1i8f8w++feWyfOa5FoNoQs67TGf5N3DtY/+vPh3qkLWvC3xqdPL/7mJuRhsXv05 o0aJpTgj0VCLuag4EQCkpWFGfAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMIsWRmVeSWpSXmKPExsVy+t9jQd0inhkhBpvOaVgsvVVtMeHydkaL s8sOslnc+NXGarHp8TVWiyP/+xktPty/yGxxfG24A4fH7IaLLB47Z91l97hzbQ+bx+Yl9R43 Xi1k8ujbsorR4/MmuQD2qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE 3FRbJRefAF23zBygm5QUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhHWMGR9P T2UrmKRVMXv5euYGxjvKXYycHBICJhI3du1hhLDFJC7cW8/WxcjFISQwnVHi1JwuVghnApPE jWW9bCBVbALaEnenb2ECsUUEZCV+/rkA1sEssIlRYsXnn6wgCWEBH4kVvQ/BilgEVCUWT1vP DGLzCrhL9L85yAKxTk5iy61H7CA2p4CHxOU5D8DqhYBqnu+5zjyBkXcBI8MqRtHUguSC4qT0 XCO94sTc4tK8dL3k/NxNjOAIeya9g3FVg8UhRgEORiUeXs606SFCrIllxZW5hxglOJiVRHgP fwYK8aYkVlalFuXHF5XmpBYfYjQFumois5Rocj4w+vNK4g2NTcyMLI3MLIxMzM2VxHmV7NtC hATSE0tSs1NTC1KLYPqYODilGhgL37rH+eYz5i7r85dz6D7QMHPns+mmOldvqDZf4MqxClvz Y86Dm2J7WiwKPm2tXT1TX/HX+3tZ55uPvjPije/d+XTSpcclfYmFxkF5NqZcrfePrBSatOdw XkGot/4MpvIz0gnzMo0kLsne35LwxKHiUDJPPsfEL0om4Q+kJdyqD0j9NuTv2q7EUpyRaKjF XFScCABaIQCdxgIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141222_042024_411937_D3EC3BB5 X-CRM114-Status: GOOD ( 12.52 ) X-Spam-Score: -5.0 (-----) Cc: ulf.hansson@linaro.org, tgih.jun@samsung.com, chris@printf.net, dianders@chromium.org, jh80.chung@samsung.com, alim.akhtar@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Seungwon Jeon Move exynos related definition to header file. And this also changes some of the registers name to match the standard naming convention. Signed-off-by: Seungwon Jeon Acked-by: Jaehoon Chung [Alim: updated the commit message] Signed-off-by: Alim Akhtar --- drivers/mmc/host/dw_mmc-exynos.c | 48 ++++---------------------------- drivers/mmc/host/dw_mmc-exynos.h | 56 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 42 deletions(-) create mode 100644 drivers/mmc/host/dw_mmc-exynos.h diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 556663f..f936704 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -21,43 +21,7 @@ #include "dw_mmc.h" #include "dw_mmc-pltfm.h" - -#define NUM_PINS(x) (x + 2) - -#define SDMMC_CLKSEL 0x09C -#define SDMMC_CLKSEL64 0x0A8 -#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) -#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) -#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) -#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) -#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ - SDMMC_CLKSEL_CCLK_DRIVE(y) | \ - SDMMC_CLKSEL_CCLK_DIVIDER(z)) -#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) - -#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 -#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 - -/* Block number in eMMC */ -#define DWMCI_BLOCK_NUM 0xFFFFFFFF - -#define SDMMC_EMMCP_BASE 0x1000 -#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) -#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) -#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) -#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) - -/* SMU control bits */ -#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7) -#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6) -#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5) -#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) -#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3) -#define DWMCI_MPSCTRL_ECB_MODE BIT(2) -#define DWMCI_MPSCTRL_ENCRYPTION BIT(1) -#define DWMCI_MPSCTRL_VALID BIT(0) - -#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */ +#include "dw_mmc-exynos.h" /* Variations in Exynos specific dw-mshc controller */ enum dw_mci_exynos_type { @@ -114,11 +78,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { mci_writel(host, MPSBEGIN0, 0); - mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); - mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT | - DWMCI_MPSCTRL_NON_SECURE_READ_BIT | - DWMCI_MPSCTRL_VALID | - DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); + mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | + SDMMC_MPSCTRL_NON_SECURE_READ_BIT | + SDMMC_MPSCTRL_VALID | + SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); } return 0; diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h new file mode 100644 index 0000000..7872ce5 --- /dev/null +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -0,0 +1,56 @@ +/* + * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver + * + * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _DW_MMC_EXYNOS_H_ +#define _DW_MMC_EXYNOS_H_ + +/* Extended Register's Offset */ +#define SDMMC_CLKSEL 0x09C +#define SDMMC_CLKSEL64 0x0A8 + +/* CLKSEL register defines */ +#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) +#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) +#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) +#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) +#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ + SDMMC_CLKSEL_CCLK_DRIVE(y) | \ + SDMMC_CLKSEL_CCLK_DIVIDER(z)) +#define SDMMC_CLKSEL_WAKEUP_INT BIT(11) + +/* Protector Register */ +#define SDMMC_EMMCP_BASE 0x1000 +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) +#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) +#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) + +/* SMU control defines */ +#define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7) +#define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3) +#define SDMMC_MPSCTRL_ECB_MODE BIT(2) +#define SDMMC_MPSCTRL_ENCRYPTION BIT(1) +#define SDMMC_MPSCTRL_VALID BIT(0) + +/* Maximum number of Ending sector */ +#define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF + +/* Fixed clock divider */ +#define EXYNOS4210_FIXED_CIU_CLK_DIV 2 +#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 + +/* Minimal required clock frequency for cclkin, unit: HZ */ +#define EXYNOS_CCLKIN_MIN 50000000 + +#endif /* _DW_MMC_EXYNOS_H_ */