| Message ID | 1420460348-20302-3-git-send-email-m.szyprowski@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
* Marek Szyprowski <m.szyprowski@samsung.com> [150105 04:22]: > All four register for latency and filter settings cannot be written in > non-secure mode and they should go through l2c_write_sec(). More on this > can be found in CoreLink Level 2 Cache Controller L2C-310 Technical > Reference Manual, 3.2. Register summary, table 3.1. This have been checked > the TRM for r3p3, but it should be uniform for all revisions. > > Reported-by: Nishanth Menon <nm@ti.com> > Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Tony Lindgren <tony@atomide.com> > --- > arch/arm/mm/cache-l2x0.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c > index 5e65ca8dea62..0aeeaa95c42d 100644 > --- a/arch/arm/mm/cache-l2x0.c > +++ b/arch/arm/mm/cache-l2x0.c > @@ -623,14 +623,14 @@ static void l2c310_resume(void) > unsigned revision; > > /* restore pl310 setup */ > - writel_relaxed(l2x0_saved_regs.tag_latency, > - base + L310_TAG_LATENCY_CTRL); > - writel_relaxed(l2x0_saved_regs.data_latency, > - base + L310_DATA_LATENCY_CTRL); > - writel_relaxed(l2x0_saved_regs.filter_end, > - base + L310_ADDR_FILTER_END); > - writel_relaxed(l2x0_saved_regs.filter_start, > - base + L310_ADDR_FILTER_START); > + l2c_write_sec(l2x0_saved_regs.tag_latency, base, > + L310_TAG_LATENCY_CTRL); > + l2c_write_sec(l2x0_saved_regs.data_latency, base, > + L310_DATA_LATENCY_CTRL); > + l2c_write_sec(l2x0_saved_regs.filter_end, base, > + L310_ADDR_FILTER_END); > + l2c_write_sec(l2x0_saved_regs.filter_start, base, > + L310_ADDR_FILTER_START); > > revision = readl_relaxed(base + L2X0_CACHE_ID) & > L2X0_CACHE_ID_RTL_MASK; > -- > 1.9.2 >
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 5e65ca8dea62..0aeeaa95c42d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -623,14 +623,14 @@ static void l2c310_resume(void) unsigned revision; /* restore pl310 setup */ - writel_relaxed(l2x0_saved_regs.tag_latency, - base + L310_TAG_LATENCY_CTRL); - writel_relaxed(l2x0_saved_regs.data_latency, - base + L310_DATA_LATENCY_CTRL); - writel_relaxed(l2x0_saved_regs.filter_end, - base + L310_ADDR_FILTER_END); - writel_relaxed(l2x0_saved_regs.filter_start, - base + L310_ADDR_FILTER_START); + l2c_write_sec(l2x0_saved_regs.tag_latency, base, + L310_TAG_LATENCY_CTRL); + l2c_write_sec(l2x0_saved_regs.data_latency, base, + L310_DATA_LATENCY_CTRL); + l2c_write_sec(l2x0_saved_regs.filter_end, base, + L310_ADDR_FILTER_END); + l2c_write_sec(l2x0_saved_regs.filter_start, base, + L310_ADDR_FILTER_START); revision = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
All four register for latency and filter settings cannot be written in non-secure mode and they should go through l2c_write_sec(). More on this can be found in CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, 3.2. Register summary, table 3.1. This have been checked the TRM for r3p3, but it should be uniform for all revisions. Reported-by: Nishanth Menon <nm@ti.com> Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- arch/arm/mm/cache-l2x0.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)