From patchwork Tue Jan 20 10:35:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 5667361 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 06DA1C058D for ; Tue, 20 Jan 2015 10:38:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B8EA20218 for ; Tue, 20 Jan 2015 10:38:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26396201B4 for ; Tue, 20 Jan 2015 10:38:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YDWB3-0005E1-Uj; Tue, 20 Jan 2015 10:36:53 +0000 Received: from bhuna.collabora.co.uk ([93.93.135.160]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YDWAT-0004tQ-R3 for linux-arm-kernel@lists.infradead.org; Tue, 20 Jan 2015 10:36:19 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: javier) with ESMTPSA id 3EB31600F46 From: Javier Martinez Canillas To: Kukjin Kim Subject: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain Date: Tue, 20 Jan 2015 11:35:26 +0100 Message-Id: <1421750127-22536-2-git-send-email-javier.martinez@collabora.co.uk> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1421750127-22536-1-git-send-email-javier.martinez@collabora.co.uk> References: <1421750127-22536-1-git-send-email-javier.martinez@collabora.co.uk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150120_023618_179076_047958CA X-CRM114-Status: UNSURE ( 9.27 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: Krzysztof Kozlowski , Kevin Hilman , Mike Turquette , Joonyoung Shim , Andrzej Hajda , linux-kernel@vger.kernel.org, Doug Anderson , Tomasz Figa , Tobias Jakobi , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sylwester Nawrocki , Olof Johansson , Marek Szyprowski , Javier Martinez Canillas , Arun Kumar K , Rahul Sharma X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas Acked-by: Sylwester Nawrocki Acked-by: Michael Turquette --- drivers/clk/samsung/clk-exynos5420.c | 23 ++++++++++++----------- include/dt-bindings/clock/exynos5420.h | 6 ++++++ 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 848d602efc06..07d666cc6a29 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP3, 0, 1), MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, SRC_TOP3, 4, 1), - MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p, - SRC_TOP3, 8, 1), + MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", + mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, SRC_TOP3, 12, 1), MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, @@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1), - MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p, - SRC_TOP5, 0, 1), + MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", + mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, SRC_TOP5, 4, 1), MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, @@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP5, 16, 1), MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, SRC_TOP5, 20, 1), - MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, - SRC_TOP5, 24, 1), + MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", + mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), @@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP10, 0, 1), MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1), - MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1), + MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, + SRC_TOP10, 8, 1), MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, SRC_TOP10, 12, 1), MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, @@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1), - MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p, - SRC_TOP12, 4, 1), + MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", + mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, SRC_TOP12, 8, 1), MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, @@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), - MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, - SRC_TOP12, 24, 1), + MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", + mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 8dc0913f1775..99da0d117a7d 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -204,6 +204,12 @@ #define CLK_MOUT_MAUDIO0 643 #define CLK_MOUT_USER_ACLK333 644 #define CLK_MOUT_SW_ACLK333 645 +#define CLK_MOUT_USER_ACLK200_DISP1 646 +#define CLK_MOUT_SW_ACLK200 647 +#define CLK_MOUT_USER_ACLK300_DISP1 648 +#define CLK_MOUT_SW_ACLK300 649 +#define CLK_MOUT_USER_ACLK400_DISP1 650 +#define CLK_MOUT_SW_ACLK400 651 /* divider clocks */ #define CLK_DOUT_PIXEL 768