From patchwork Fri Jan 23 16:08:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Ribalda Delgado X-Patchwork-Id: 5695971 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3B6F5C058D for ; Fri, 23 Jan 2015 16:22:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4B4132028D for ; Fri, 23 Jan 2015 16:22:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 734D1201F4 for ; Fri, 23 Jan 2015 16:22:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YEgwz-0003MJ-6r; Fri, 23 Jan 2015 16:19:13 +0000 Received: from mail-lb0-x22d.google.com ([2a00:1450:4010:c04::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YEgnd-00035F-Ne for linux-arm-kernel@lists.infradead.org; Fri, 23 Jan 2015 16:09:37 +0000 Received: by mail-lb0-f173.google.com with SMTP id p9so3504720lbv.4 for ; Fri, 23 Jan 2015 08:09:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=msQqLpqzf5Rg1TF91YwyuviM5A/yc6e2rZQq9+LDhWc=; b=O2emPECjaBcq8a1PUnDT3XJS/K57hcbGobA1LoV6EGT+xdXDE8S5t2e0XSbeuBEa76 HzfL3lDjZxXSpsgiErA6pCR23+2RC3TxCkyjKexTsQu+3G4eMeM4XPE1lhXg1Ntu5REV 3+Z13LvkMBb2UsMqrLBubbYyOTe9yrf9Wki5w3nQF9xc2lEtc/Qrg0UxZs6gFy3oxmNL qlzPYs8vHK4kFJBBYDowbPF1X8oEqozITB9HhKMdyTK3JsCoUFbjSWpPk+KCbtX3wpcw bD35EaOzmzFD0QJfqGkP2unrvu0rFzVzyO6tCRvLUrwsfrODU0tdn00cUYYbvo2aSz16 es/g== X-Received: by 10.112.183.197 with SMTP id eo5mr8049728lbc.81.1422029349862; Fri, 23 Jan 2015 08:09:09 -0800 (PST) Received: from neopili.qtec.com (cpe.xe-3-0-1-778.vbrnqe10.dk.customer.tdc.net. [80.197.57.18]) by mx.google.com with ESMTPSA id h7sm542990lbl.41.2015.01.23.08.09.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 Jan 2015 08:09:08 -0800 (PST) From: Ricardo Ribalda Delgado To: Mark Brown , Michal Simek , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/18] spi/xilinx: Support for spi mode CS_HIGH Date: Fri, 23 Jan 2015 17:08:42 +0100 Message-Id: <1422029330-10971-11-git-send-email-ricardo.ribalda@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1422029330-10971-1-git-send-email-ricardo.ribalda@gmail.com> References: <1422029330-10971-1-git-send-email-ricardo.ribalda@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150123_080934_007269_4EBD2E4A X-CRM114-Status: GOOD ( 16.63 ) X-Spam-Score: -0.8 (/) Cc: Ricardo Ribalda Delgado X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The core controls the chip select lines individually. By default, all the lines are consider active_low. After spi_setup_transfer, it has its real value. Signed-off-by: Ricardo Ribalda Delgado --- drivers/spi/spi-xilinx.c | 62 +++++++++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 24 deletions(-) diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c index a70cb91..29edf1b 100644 --- a/drivers/spi/spi-xilinx.c +++ b/drivers/spi/spi-xilinx.c @@ -89,6 +89,7 @@ struct xilinx_spi { int remaining_bytes; /* the number of bytes left to transfer */ u8 bits_per_word; int buffer_size; /* buffer size in words */ + u32 cs_inactive; /* Level of the CS pins when inactive*/ unsigned int (*read_fn)(void __iomem *); void (*write_fn)(u32, void __iomem *); void (*tx_fn)(struct xilinx_spi *); @@ -194,33 +195,37 @@ static void xspi_init_hw(struct xilinx_spi *xspi) static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) { struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); + u16 cr; + u32 cs; if (is_on == BITBANG_CS_INACTIVE) { /* Deselect the slave on the SPI bus */ - xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); - } else if (is_on == BITBANG_CS_ACTIVE) { - /* Set the SPI clock phase and polarity */ - u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) - & ~XSPI_CR_MODE_MASK; - if (spi->mode & SPI_CPHA) - cr |= XSPI_CR_CPHA; - if (spi->mode & SPI_CPOL) - cr |= XSPI_CR_CPOL; - if (spi->mode & SPI_LSB_FIRST) - cr |= XSPI_CR_LSB_FIRST; - if (spi->mode & SPI_LOOP) - cr |= XSPI_CR_LOOP; - xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); - - /* We do not check spi->max_speed_hz here as the SPI clock - * frequency is not software programmable (the IP block design - * parameter) - */ - - /* Activate the chip select */ - xspi->write_fn(~(0x0001 << spi->chip_select), - xspi->regs + XSPI_SSR_OFFSET); + xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); + return; } + + /* Set the SPI clock phase and polarity */ + cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; + if (spi->mode & SPI_CPHA) + cr |= XSPI_CR_CPHA; + if (spi->mode & SPI_CPOL) + cr |= XSPI_CR_CPOL; + if (spi->mode & SPI_LSB_FIRST) + cr |= XSPI_CR_LSB_FIRST; + if (spi->mode & SPI_LOOP) + cr |= XSPI_CR_LOOP; + xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); + + /* We do not check spi->max_speed_hz here as the SPI clock + * frequency is not software programmable (the IP block design + * parameter) + */ + + cs = xspi->cs_inactive; + cs ^= BIT(spi->chip_select); + + /* Activate the chip select */ + xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); } /* spi_bitbang requires custom setup_transfer() to be defined if there is a @@ -229,6 +234,13 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) static int xilinx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { + struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); + + if (spi->mode & SPI_CS_HIGH) + xspi->cs_inactive &= ~BIT(spi->chip_select); + else + xspi->cs_inactive |= BIT(spi->chip_select); + return 0; } @@ -369,9 +381,11 @@ static int xilinx_spi_probe(struct platform_device *pdev) return -ENODEV; /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | + SPI_CS_HIGH; xspi = spi_master_get_devdata(master); + xspi->cs_inactive = 0xffffffff; xspi->bitbang.master = master; xspi->bitbang.chipselect = xilinx_spi_chipselect; xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;