From patchwork Fri Jan 30 05:13:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Henry Chen X-Patchwork-Id: 5746571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A6834BF440 for ; Fri, 30 Jan 2015 05:17:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DB141201F4 for ; Fri, 30 Jan 2015 05:17:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C3C6201DD for ; Fri, 30 Jan 2015 05:17:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YH3ty-00048j-4j; Fri, 30 Jan 2015 05:13:54 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YH3tu-00046Z-Am for linux-arm-kernel@lists.infradead.org; Fri, 30 Jan 2015 05:13:51 +0000 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1404038174; Fri, 30 Jan 2015 13:13:22 +0800 Received: from mtksdtcf10.mediatek.inc (10.21.12.150) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Fri, 30 Jan 2015 13:13:21 +0800 From: Henry Chen To: Rob Herring , Matthias Brugger , Mike Turquette Subject: [PATCH v4 7/7] dts: mediatek: Enable clock support for Mediatek MT8173. Date: Fri, 30 Jan 2015 13:13:18 +0800 Message-ID: <1422594798-13375-8-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1422594798-13375-1-git-send-email-henryc.chen@mediatek.com> References: <1422594798-13375-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150129_211350_600221_96EA38FC X-CRM114-Status: UNSURE ( 7.71 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.3 (+) Cc: Mark Rutland , jamesjj.liao@mediatek.com, Vladimir Murzin , Russell King , srv_heupstream@mediatek.com, Pawel Moll , Ian Campbell , Catalin Marinas , linux-kernel@vger.kernel.org, henryc.chen@mediatek.com, devicetree@vger.kernel.org, Ashwin Chaugule , Sascha Hauer , Kumar Gala , "Joe.C" , eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: James Liao This patch adds MT8173 clock controllers into device tree. Signed-off-by: James Liao Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 41c1441..31ccad3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include + / { compatible = "mediatek,mt8173"; interrupt-parent = <&sysirq>; @@ -78,6 +80,26 @@ affinity_info = <0x84000004>; }; + clocks { + clk_null: clk_null { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clk26m: clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk32k: clk32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + uart_clk: dummy26m { compatible = "fixed-clock"; clock-frequency = <26000000>; @@ -99,6 +121,24 @@ compatible = "simple-bus"; ranges; + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8173-infracfg"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: pericfg@10003000 { + compatible = "mediatek,mt8173-pericfg"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -107,6 +147,12 @@ reg = <0 0x10200620 0 0x20>; }; + apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10220000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;