From patchwork Fri Jan 30 23:53:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 5753371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 763349F38B for ; Fri, 30 Jan 2015 23:56:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A38502027D for ; Fri, 30 Jan 2015 23:56:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96AA120274 for ; Fri, 30 Jan 2015 23:56:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YHLOE-0005Yb-OX; Fri, 30 Jan 2015 23:54:18 +0000 Received: from mail.kmu-office.ch ([2a02:418:6a02::a2]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YHLOB-0005Tm-OM for linux-arm-kernel@lists.infradead.org; Fri, 30 Jan 2015 23:54:16 +0000 Received: from trochilidae.toradex.int (195-226-23-137.pool.cyberlink.ch [195.226.23.137]) by mail.kmu-office.ch (Postfix) with ESMTPSA id 8FC045C0026; Sat, 31 Jan 2015 00:51:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=agner.ch; s=dkim; t=1422661905; bh=k0hhe6NDR7w4thPE1poUW4CyfART8Xq147+3JkiEdmY=; h=From:To:Cc:Subject:Date:From; b=KtjldFMP/9+jt6Dn1DwyCEqqEIPVR7EhpJu+1G7BUQNP0SgV/QyD/gh6/rGjojLxg if3jK9h3hcHr/oN28xwOHiz6tChWIFf0kBb0r7rktJzNv/Fd4AabaWkq4wwAiFVOf6 BZ0C4Po0d7Atl3gQ7+O4S4p3Loln3XArVlQIpMug= From: Stefan Agner To: linux@arm.linux.org.uk Subject: [PATCH] ARM: extend SMP_ON_UP detection for A5 MPCore devices with 1 CPU Date: Sat, 31 Jan 2015 00:53:46 +0100 Message-Id: <1422662026-12968-1-git-send-email-stefan@agner.ch> X-Mailer: git-send-email 2.2.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150130_155415_969326_EA342F1A X-CRM114-Status: GOOD ( 11.42 ) X-Spam-Score: -0.1 (/) Cc: linux-kernel@vger.kernel.org, stefan@agner.ch, r.sricharan@ti.com, santosh.shilimkar@ti.com, vaibhav.bedia@ti.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On the non-SMP Cortex-A5 Vybrid SoC detection of SMP_ON_UP fails. Some variants of this SoC have a secondary Cortex-M4 CPU, which might be the reason the MPIDR register reporting a multiprocessor system. The code introduced in bc41b8724f ("ARM: 7846/1: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices") proved applicable for Vybrid too: The SCU register number of CPUs reports b00 indicating only one A5 MPCore being present in the system. This patch lets Cortex-A5 CPU's use the SCU check too. On the Vybrid platform this did not lead to CPU faults (so far), but is_smp checks evaluate to true which is not optimal performance wise. Signed-off-by: Stefan Agner --- A boot log of the Vybrid SoC with this patch applied is available at: http://www.agner.ch/vybrid-vf610-3.19-rc6-smp-fixup.txt arch/arm/kernel/head.S | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 664eee8..35982af 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -492,19 +492,24 @@ __fixup_smp: mrc p15, 0, r0, c0, c0, 5 @ read MPIDR and r0, r0, #0xc0000000 @ multiprocessing extensions and teq r0, #0x80000000 @ not part of a uniprocessor system? - bne __fixup_smp_on_up @ no, assume UP + bne __fixup_smp_on_up @ no, assume UP - @ Core indicates it is SMP. Check for Aegis SOC where a single - @ Cortex-A9 CPU is present but SMP operations fault. + @ Core indicates it is SMP. Check for Vybrid/Aegis SoC where a single + @ Cortex-A5/A9 CPU is present mov r4, #0x41000000 orr r4, r4, #0x0000c000 - orr r4, r4, #0x00000090 - teq r3, r4 @ Check for ARM Cortex-A9 - retne lr @ Not ARM Cortex-A9, - + orr r0, r4, #0x00000090 + teq r3, r0 @ Check for ARM Cortex-A9 + beq __fixup_smp_by_scu + orr r0, r4, #0x00000050 + teq r3, r0 @ Check for ARM Cortex-A5 + beq __fixup_smp_by_scu + ret lr @ Not ARM Cortex-A5 or A9, assume SMP + +__fixup_smp_by_scu: @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the @ below address check will need to be #ifdef'd or equivalent - @ for the Aegis platform. + @ for the Vybrid and Aegis platform. mrc p15, 4, r0, c15, c0 @ get SCU base address teq r0, #0x0 @ '0' on actual UP A9 hardware beq __fixup_smp_on_up @ So its an A9 UP