diff mbox

[1/3] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts

Message ID 1423116037-5921-1-git-send-email-wenyou.yang@atmel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Wenyou Yang Feb. 5, 2015, 6 a.m. UTC
From: Sylvain Rochet <sylvain.rochet@finsecur.com>

Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
something went wrong instead of continuing in unknown condition. There
is not much we can do if a PLL lock never ends, we are running in SRAM
and we will not be able to connect back the sdram or ddram in order to
be able to fire up a message or just panic.

As a bonus, not decounting the timeout register in slow clock mode
reduce cumulated suspend time and resume time from ~17ms to ~15ms.

Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>
---
 arch/arm/mach-at91/pm_slowclock.S |   33 ++++-----------------------------
 1 file changed, 4 insertions(+), 29 deletions(-)

Comments

Nicolas Ferre March 3, 2015, 6:41 p.m. UTC | #1
Le 05/02/2015 07:00, Wenyou Yang a écrit :
> From: Sylvain Rochet <sylvain.rochet@finsecur.com>
> 
> Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
> something went wrong instead of continuing in unknown condition. There
> is not much we can do if a PLL lock never ends, we are running in SRAM
> and we will not be able to connect back the sdram or ddram in order to
> be able to fire up a message or just panic.
> 
> As a bonus, not decounting the timeout register in slow clock mode
> reduce cumulated suspend time and resume time from ~17ms to ~15ms.
> 
> Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
> Acked-by: Wenyou.Yang <wenyou.yang@atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

and stacked in at91-4.0-fixes.
thanks!

> ---
>  arch/arm/mach-at91/pm_slowclock.S |   33 ++++-----------------------------
>  1 file changed, 4 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index 2001877..79dfdbe 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
> @@ -34,11 +34,6 @@
>   */
>  #undef SLOWDOWN_MASTER_CLOCK
>  
> -#define MCKRDY_TIMEOUT		1000
> -#define MOSCRDY_TIMEOUT 	1000
> -#define PLLALOCK_TIMEOUT	1000
> -#define PLLBLOCK_TIMEOUT	1000
> -
>  pmc	.req	r0
>  sdramc	.req	r1
>  ramc1	.req	r2
> @@ -50,56 +45,36 @@ tmp2	.req	r5
>   * Wait until master clock is ready (after switching master clock source)
>   */
>  	.macro wait_mckrdy
> -	mov	tmp2, #MCKRDY_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_MCKRDY
>  	beq	1b
> -2:
>  	.endm
>  
>  /*
>   * Wait until master oscillator has stabilized.
>   */
>  	.macro wait_moscrdy
> -	mov	tmp2, #MOSCRDY_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_MOSCS
>  	beq	1b
> -2:
>  	.endm
>  
>  /*
>   * Wait until PLLA has locked.
>   */
>  	.macro wait_pllalock
> -	mov	tmp2, #PLLALOCK_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_LOCKA
>  	beq	1b
> -2:
>  	.endm
>  
>  /*
>   * Wait until PLLB has locked.
>   */
>  	.macro wait_pllblock
> -	mov	tmp2, #PLLBLOCK_TIMEOUT
> -1:	sub	tmp2, tmp2, #1
> -	cmp	tmp2, #0
> -	beq	2f
> -	ldr	tmp1, [pmc, #AT91_PMC_SR]
> +1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
>  	tst	tmp1, #AT91_PMC_LOCKB
>  	beq	1b
> -2:
>  	.endm
>  
>  	.text
>
diff mbox

Patch

diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 2001877..79dfdbe 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -34,11 +34,6 @@ 
  */
 #undef SLOWDOWN_MASTER_CLOCK
 
-#define MCKRDY_TIMEOUT		1000
-#define MOSCRDY_TIMEOUT 	1000
-#define PLLALOCK_TIMEOUT	1000
-#define PLLBLOCK_TIMEOUT	1000
-
 pmc	.req	r0
 sdramc	.req	r1
 ramc1	.req	r2
@@ -50,56 +45,36 @@  tmp2	.req	r5
  * Wait until master clock is ready (after switching master clock source)
  */
 	.macro wait_mckrdy
-	mov	tmp2, #MCKRDY_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_MCKRDY
 	beq	1b
-2:
 	.endm
 
 /*
  * Wait until master oscillator has stabilized.
  */
 	.macro wait_moscrdy
-	mov	tmp2, #MOSCRDY_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_MOSCS
 	beq	1b
-2:
 	.endm
 
 /*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
-	mov	tmp2, #PLLALOCK_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_LOCKA
 	beq	1b
-2:
 	.endm
 
 /*
  * Wait until PLLB has locked.
  */
 	.macro wait_pllblock
-	mov	tmp2, #PLLBLOCK_TIMEOUT
-1:	sub	tmp2, tmp2, #1
-	cmp	tmp2, #0
-	beq	2f
-	ldr	tmp1, [pmc, #AT91_PMC_SR]
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
 	tst	tmp1, #AT91_PMC_LOCKB
 	beq	1b
-2:
 	.endm
 
 	.text